We develop a design methodology for mapping computer vision algorithms onto an FPGA through the use of coarse-grain reconfigurable dataflow graphs as a representation to guide the designer. We first describe a new dataflow modeling technique called homogeneous parameterized dataflow (HPDF), which effectively captures the structure of an important class of computer vision applications. This form of dynamic dataflow takes advantage of the property that in a large number of image processing applications, data production and consumption rates can vary, but are equal across dataflow graph edges for any particular application iteration. After motivating and defining the HPDF model of computation, we develop an HPDF-based design methodology that offers useful properties in terms of verifying correctness and exposing performance-enhancing transformations; we discuss and address various challenges in efficiently mapping an HPDF-based application representation into target-specific HDL code; and we present experimental results pertaining to the mapping of a gesture recognition application onto the Xilinx Virtex II FPGA.

A wide variety of DSP design tools have been developed that incorporate dataflow graph representations into their GUI-based design environments.However, as the complexity of application graph topologies increases, textual manipulation of graph specifications becomes increasingly important. The dataflow interchange format (DIF) provides a text-based language for the description of dataflow graphs. Currently, the DIF infrastructure supports the specification of mixed-grain dataflow models, porting of dataflow applications specified in DIF across DSP design tools, software synthesis of applications specified in DIF, as well as a variety of optimization and analysis capabilities. This paper presents a novel set of dataflow graph configuration features that have been developed in the DIF language. These features greatly enhance the flexibility and power with which dataflow graphs, especially large-scale graphs, can be constructed and manipulated in DIF. To support the new graph configuration capabilities, several new concepts have been incorporated into the DIF language semantics, such as the capability to handle certain dynamic dataflow constructs, and support for C-like arrays in DIF specifications. Along with these concepts, a new framework for the construction and manipulation of DIF objects through the use of C/C++ is presented, and applications of this framework are demonstrated.

We develop a design methodology for mapping computer vision algorithms onto an FPGA through the use of coarse-grain reconfigurable dataflow graphs as a representation to guide the designer. We first describe a new dataflow modeling technique called homogeneous parameterized dataflow (HPDF), which effectively captures the structure of an important class of computer vision applications. This form of dynamic dataflow takes advantage of the property that in a large number of image processing applications, data production and consumption rates can vary, but are equal across dataflow graph edges for any particular application iteration. After motivating and defining the HPDF model of computation, we develop an HPDF-based design methodology that offers useful properties in terms of verifying correctness and exposing performance-enhancing transformations; we discuss and address various challenges in efficiently mapping an HPDF-based application representation into target-specific HDL code; and we present experimental results pertaining to the mapping of a gesture recognition application onto the Xilinx Virtex II FPGA.

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