Abstract-New back-end design for manufacturability rules have brought guarantee rules for interconnect matching. These rules indicate a certain capacitance matching guarantee given spacing between interconnects and interconnect area. Yet, the number of these rules is so few that they are of limited value in circuit or interconnect optimization. A method to infer additional guarantees from the provided guarantees is necessary so that optimization can be optimal. In this paper, we target two problems. First, we present a methodology to infer additional matching guarantees through extracting correlation information from the given limited set of matching guarantees in the design manual. In order to achieve this, we propose a multi-function variant of multi-variate Newton-Raphson method to extract parameters of the proposed dimension-and distancebased process correlation model for interconnects. We propose to use the extracted correlation information to infer a continuum of matching rules through simulation with proposed modifications to the standard capacitance extraction procedure. Secondly, we show how to directly incorporate the inferred interconnect matching guarantees for accurate interconnect optimization in a flexible geometric programming construction. We show how much resource savings are possible through inferring of new matching rules. Applying the inferred mismatch guarantees allows a geometric programming-based H-tree optimization to reduce the clock tree resources 27% on average and up to 56%.
Variability of electrical parameters across the product die and wafer compromises functionality and yield of integrated device families in the sub-100-nm technologies, such as System-on-Chip. We discuss variability reduction through: Tightening manufacturing process variability, design-for-manufacturability ͑DFM͒ rules, and parameterized, correct-byconstruction ͑CBC͒ layout. While so far the best option for variability reduction has been to improve process capability without impacting product design, it may no longer be preferred due to continuously increasing processes cost driven by technology shrinks. Currently, the CBC parametric layout emerges as the best option, with parametric variability traded for device footprint or the aggressiveness of the resolution enhancement techniques ͓e.g., optical proximity correction ͑OPC͔͒. The least favorable from the product flow standpoint is the layout-time addition of design rules or OPC in response to the localized issues in a random layout ͑hot spots͒, which causes reworks and delays, or compromises the process window. For the optimal parameterized layout, we discuss rule development for MOSFET gate length variation and dummy device placement. In summary, a number of tradeoffs are necessary for the design optimization to minimize device variability, depending on the product application.
Technology, CAD, and design are increasingly more challenged by Design-for-Manufacturability rules and guidelines required to improve pattern transfer quality to the reticle and silicon wafer. One key reason for this challenge is the variability of the layout, which for SoC designs beyond the 100 nm technology node should no longer be subject only to short range design rule checks concerning individual layout features. To include the impact of medium and long-range pattern interactions (across-die or exposure field) into the design process, one should change layout architecture methodology distributed so far among technology, CAD, and design groups and using manual drawing techniques or semiautomated tools with different quality standards. This task becomes even more important for the SoC layout for analog/RF applications where signal propagation is sensitive to device matching requirements and capacitive coupling. At that point, IC designer had two options to control the layout freedom: by enforcing new, more restrictive design rules or by using parameterized layout based on standard cells proven on silicon, including all electrically extracted RET, OPC, and dummy features. In this work, we will show that the standardized layout is the preferred option leading to the improved quality, reduced cycletime, and higher yields.
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