Complex real-time signal and image processing applications require low-latency and high-performance hardware to achieve optimal performance. Building such a high-performance platform for space deployment is hampered by hostile environmental conditions and power constraints. Custom space-based FPGA coprocessors help alleviate these constraints, but their use is typically restricted by the need for TMR or radiation-hardened components. This paper 12 explores a framework that allows earth and space scientists to use FPGA resources through an abstraction layer. A synthetic aperture radar application is used to demonstrate the power of the system architecture. The performance of the application is shown to achieve a speedup of 19 when compared to a software solution and is able to maintain comparable data reliability. Projected speedups, for the same case study executing on the proposed flight system architecture, are several times better and also discussed.This work supports the Dependable Multiprocessor project at Honeywell and the University of Florida, a mission for the Space Technology 8 (ST-8) satellite of NASA's New Millennium Program.

With the ever-increasing demand for higher bandwidth and processing capacity of today's space exploration, space science, and defense missions, the ability to efficiently apply Commercial-Off-The-Shelf (COTS) processors for on-board computing has become a critical need. In response to this need, NASA's New Millennium Program (NMP) office commissioned the development of Dependable Multiprocessor (DM) technology for use in science and autonomy missions, but the technology is also applicable to a wide variety of DoD missions. The goal of the DM project is to provide spacecraft/payload processing capability 10x -100x what is available today, enabling heretofore unrealizable levels of science and autonomy. DM technology is being developed as part of the NMP ST8 (Space Technology 8) project. The objective of this NMP ST8 effort is to combine high-performance, fault tolerant, COTS-based cluster processing and fault tolerant middleware in an architecture and software framework capable of supporting a wide variety of mission applications. Dependable Multiprocessor development is continuing as one of the four selected ST8 flight experiments planned to be flown in 2009. 1, 2, 3There are three key problems that need to be overcome in order to fly COTS in space: 1) an effective approach for handling SEUs (Single Event Upsets) in high performance cluster processors, 2) handling thermal issues associated with state-of-the-art COTS components, and 3) achieving high power efficiency (throughput per watt). DM technology solves all three problems. DM solves the SEU problem by combining cluster management software with SEU tolerance-enhancing software in a flexible, efficient, integrated DM middleware suite. DM solves the thermal 1 1-4244-The project formerly was known as the Environmentally-Adaptive FaultTolerant Computing (EAFTC) project. issue by mining the ruggedized, conductive-cooled, COTS airborne embedded processing domain. DM solves the power efficiency problem by mining the high performance, low power mobile computing processing domain.Recently, the DM project successfully passed several key NMP ST8 project milestones: the TRL5 (Technology Readiness Level 5) technology validation demonstration, the Experiment Preliminary Design Review, and the NASA Non Advocate Review. Passing the TRL5 milestone qualified the DM project for advancement to flight system development status. The ST8 project has passed its Preliminary Design and Confirmation Reviews and is now moving into the Implementation Phase.This paper describes the DM technology, the technology validation experiments and demonstrations achieved to date, the plans for the TRL6 technology validation effort, and the plans for the TRL7 flight validation, and provides an update on the status of the project TABLE OF CONTENTS