This paper considers a modified variant of the lossless digital integrator lattice filter structure presented in [l, 2, 31, which in [l] is also labeled lattice bilinear digital ladder filter (BDLF). It is shown that the structure easily can be modified so that the critical loop reduces from two multipliers to one. This has the potential of significantly improving the computational speed when the filter is implemented directly in hardware. Two test filters of the modified BDLF structure are compared to three-port circulator lattice wave digital filters (WDF), which also have critical loops of only one multiplier. It is shown that for the test filters, the BDLF realizations are similar to the WDF realizations regarding multiplier wordlength requirements, while they are superior regarding quantization noise and structural complexity.

No abstract

No abstract

In this paper we study digit-serial implementation of the general-order lossless discrete integrator/differentiator (LDI/LDD) allpass filter structure. In low-power filter implementation, digit-serial computation has been shown to be advantageous compared to bit-serial and parallel arithmetics [l]. The digit-serial processing elements are obtained using unfolding techniques. The implementation is compared to a corresponding wave digital (WD) implementation. It is shown in an example that a WD realization requires about 60% and 30% more D flip-flops for pipelining and shimming delays, respectively, than the corresponding LDI/LDD implementation. We also study the sample period of the second-order LDI/LDD allpass filter using different digit sizes and conclude that when the filter is scheduled over a number of sample periods we achieve the shortest sample period.

No abstract