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A 3.3-V CMOS technology with 0.6-pm design rules in sixth-generation twin-tub CMOS (twin-tub VI) has been developed. The major features of the device in this technology are: HIPOX twin-tub structure, n+ /p' dual-type poly gate, 125-A thin gate oxide, shallow junctions, RTA activation, and thin TiSit as source/drain/gate silicide layer. Electrical measurements show good I-V characteristics, ideal low junction leakage, latchup immunity for 4.5-pm n+-to-p+ spacing, more than 6.0-V NMOSFET snapback breakdown voltage, good hot-carrier aging properties, and undetectable dopant inter-lat-era1 diffusion through a TiSi2 shunt layer of a different type of poly. The transistors have been scaled to 0.45-asd 0.40-pm effective channel length, without punchthrough at Vds = 3.6 Y for NMOS and PMOS, respectively. A 100-ps stage delay is obtained on a 101-stage CMOS ring oscillator at an operating voltage of 3.3 V.

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