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In order to use silicon as an efficient thermoelectric (TE) material for TE energy conversion, it is necessary to reduce its relatively high thermal conductivity, while maintaining the high power factor. This can be done by structuring silicon into 1-D structures or nanowires (NWs). Due to nanostructuring phonon scattering with the surface of such wires is drastically increased. This can result in a reduction of the thermal conductivity at a factor of 100 with respect to bulk silicon. Fabrication of vertical silicon NWs using ICP-cryogenic dry etching (Inductive Coupled Plasma) is described as a concept for CMOS-compatible integration of NW arrays instead of single NWs into a TE converter device. The uniform height of the NWs allows to connect simultaneously all NWs of an array. The realized NWs have diameters down to 180 nm and their height was selected between 1 and 10 l. Measurement of electrical and thermal resistance of single silicon NWs with different diameters will be presented which was done in a scanning electron microscope (SEM) equipped with nanomanipulators. Furthermore, measurements will be shown of the thermal conductivity and the Seebeck coefficient of NW arrays.