No abstract

Built In Self Test for FPGAs has become an important area of research over the years. The current research focuses on the use ofJHDL as an implementation tool for BIST The research spans the design, simulation and JHDL implementation of a BIST scheme for testing the Look-Up Tables ofa Xilinx SRAM based Spartan II FPGA. To the best of our knowledge, this is the first attempt by any researcher in using JHDL for implementing BIST on FPGAs.

In chaos-based spread spectrum systems, the use of spreading code and chaotic binary sequence expands the bandwidth of the information-bearing signal but this expansion results in SNR degradation under the constraint of constant channel capacity according to Hartley-Shannon law. To compensate for this drawback, our proposed model employs an irregular low-density parity-check (LDPC) code with its iterative decoding algorithm. Coupled with this forward error correction (FEC) coding, we used non-coherent (NC) 16-ary differential chaos shift keying (16-DCSK) that additionally provides the ability of data encryption due to its use of chaotic signals compared with the conventional modulation schemes. Analytical expressions of bit error probability (BEP) are derived under the assumption of the three-ray model along with partial band noise jamming (PBNJ) over a Rayleigh fading channel. Simulation results assert that the proposed system can mitigate the effect of PBNJ via lowering BEP by coding gain and processing gain under identical transmission power. It is also confirmed that a higher level of security can be provided by the use of proposed two iteration functions of Duffing Map-based chaotic binary sequence than the security level of one iteration function of Logistic Map, based on the balance and autocorrelation analysis.

No abstract

No abstract