This paper describes a 32-bit superscalar microprocessor GMICRO/4OO, based on the TRON architecture specifications. The GM1C~0/400 has a dual issued instruction pipeline, a pre-jump mechanism and a high-speed memory access interface. To realize high performance in processing of series data such as frame buffer o r character-strings, the GMICRO/400 has improved the execution efficiency of multiple-operation instructions by blockdata-transfer and Wbit processing. In order to improve the task switching latency, the onchip caches are used as a local memory in which the context blocks are stored. These techniques are suitable for realtime embedded systems, such as X-window terminals and printers.Using 05pm triple-layer metal CMOS technology, the GMICRO/4OO integrates 1485K transistors on a 108mm2 die area. The Gh11C~0/400 achieves a processing speed of 45 MIPS at 40MHz.

No abstract

No abstract

This paper describes the architecture and implementation of the application specific processor, the GlOOFTS, designed for faulttolerant systems. The GlOOFTS integrates the core-processor and the support module for fault-tolerant operation. The core-processor is the 32-bit microprocessor Gmicro/lOO based on the TRON specifications. The support module provides a mechanism of error detection, a rollback operation that recovers a processor from a transient fault, diagnosis of faulty processors, and reconfiguration of a single processor system to make it operate continuously. The GlOOFTS drastically reduces the component count of a system, and provides high system reliability. The GlOOFTS performs all the fault-tolerant operations in hardware and requires no dedicated programs for fault-tolerance. The chip contains 805K transistors withim a chip size of 13 mm x 14 nun. A 1.0-micron, double metal CMOS technology has been used.

No abstract