No abstract

No abstract

A CMOS widely tunable second-order Gm-C bandpass filter (BPF), intended to be used in multi-sine bioimpedance applications, is presented. The filter incorporates a tunable transconductor in which the responses of two linearized voltage-to-current converters are subtracted. As a result, the effective transconductance can be continuously adjusted over nearly three decades, which allows a corresponding programmability of the center frequency of the BPF. The circuit was designed and fabricated in 180 nm CMOS technology to operate with a 1.8 V supply, and the experimental characterization was carried out over eight samples of the silicon prototype. The simulated transconductance of the cell can be tuned from 5.3 nA/V up to 19.60 μA/V. The measured range of the experimental transconductance varied, however, between 1.42 μA/V and 20.57 μA/V. Similarly, the center frequency of the BPF, which in the simulations ranged from 500 Hz to 342 kHz, can be programmed in the silicon prototypes from 22.4 kHz to 290 kHz. Monte Carlo and corner simulations were carried out to ascertain the origin of this deviation. Besides, the extensive simulation and experimental characterization of the standalone transconductor and the complete BPF are provided.

The design of an instrumentation amplifier (IA), based on indirect current feedback and suited to electrical bioimpedance spectroscopy, is presented. The IA consists of two transconductors and a summing stage, featuring a single-stage configuration process that allows the maximum achievable bandwidth to be extended. The transconductors are linearized by means of resistive source degeneration, whereas the use of super source followers allows a reduction in the values of the source degeneration resistors. This fact leads to a decrease in the overall noise and the silicon area, thus resulting in a compact implementation. A thorough analysis of the proposed solution, accompanied by a design procedure and verified by means of electrical simulations, is also provided. Two versions of the IA, i.e., a single-ended (SE) and a pseudo-differential (PD) structure, were designed and fabricated using 180 nm CMOS technology to operate with a 1.8 V supply. The experimental results, including a BW of 5.2 MHz/8.0 MHz, a CMRR higher than 72 dB/80 dB, a DC current consumption of 139.0 μA/219.3 μA and a silicon area equal to 0.0173 mm2/0.0291 mm2 for the SE/PD implementation, validate the suitability of the approach.

No abstract