This study investigated the effects of Si wafer polish damage on the electrical performance and integrated circuits, using metal-oxide-semiconductor capacitors as the test structures. These test capacitors were fabricated with 100 or 250 Å oxide layers thermally grown on wafers having varied polish-damaged surfaces. Field-dependent and time-dependent breakdown data were measured and correlated with the surface polish quality as characterized by thermal wave (TW) modulated reflectance measurements. To study the effects of damage remaining in the silicon beneath the Si/SiO2 interface after the formation of the capacitors, the minority-carrier lifetime was measured and also correlated with the TW values obtained on the starting (nonprocessed) wafer surfaces. The results of this study established that increased polish damage, indicated by higher TW values, adversely affects thin oxide breakdown integrity and reduces the minority-carrier lifetime.

Various pre-gate oxide cleaning and gettering techniques on the integrity of thin gate oxide were investigated. A 100 Å thick oxide capacitor was used to study its time-dependent breakdown characteristics and minority carrier lifetime. It has been shown that the oxide integrity as measured by time-dependent breakdown and the minority carrier lifetime are very sensitive to the cleaning technique. On the other hand, given adequate cleaning process, different intrinsic gettering schemes may only influence the oxygen precipitation, as well as the minority carrier lifetime, but not the oxide integrity.

Effects of post-well drive intrinsic gettering (PWIG) upon the integrity of thin gate oxide in Cz Si wafers with carbon levels, Cs, ranged from 0.2 - ∼ 4 ppma were investigated. A 10 nm thick gate oxide capacitor was used to study its time-dependent breakdown characteristics and minority carrier lifetime. Our data have shown that PWIG cycles and/or carbon impurity affect both bulk oxygen precipitation and minority carrier lifetime, but not the oxide integrity.