A leading edge 90 nm technology with 1.2 nm physical gate oxide, SO nm gate length, strained silicon, NiSi, 7 layers of Cu interconnects, and low k CDO for high performance dense logic is presented. Strained silicon is used to increase saturated NMOS and PMOS drive currents by 10-20% and mobility by > 50%. Aggressive design rules and unlanded contacts offer a l.0pm2 6-T S R A M cell using 193nm lithography. IntroductionThe power dissipation of modern microprocessors has been rapidly increasing, driven by increasing transistor count and clock frequencies. The rapidly increasing power has occurred even though the power per gate switching transition has decreased approximately (0.7)' per technology node due to voltage scaling and device area scaling. Figure 1 shows these trends for Intel's microprocessors and CMOS logic technology generations. In this paper we describe a 90 nm generation technology designed for high speed and low power operation. Strained silicon channel transistors are used to obtain the desired performance at 1.0V to 1.2V operation. renw 5 B 0 n 1 0 0 0 0~ Pentiud U) E 1.5 1 0.8 0.6 0.35 0.25 0.18 0.13 Technology (pm) Figure 1: Power and transistor switching energy trends. procesS Flow and Technology FeaturesFront-end technology features include shallow trench isolation, retrograde wells, shallow abrupt sourceldrain extensions, halo implants, deep sourcddrain, and nickel salicidation. N-wells and P-wells are formed with deep phosphw rous and shallow arsenic implants, and boron implants respectively. The trench isolation is 400 nm deep to provide robust inma-and inter-well isolation for N+ to P+ spacing below 240 nm while maintaining low junction capacitance. Sidewall spacers are formed with CVD Si,N4 deposition, followed by etch-back. Shallow sourcedrain extension regions are formed with arsenic for NMOS and boron for PMOS. Nisi is formed on poly-silicon gate and source-drain regions to provide low contact resistance.

We present the experimental demonstration of a subaperture compression scheme achieved in the PETAL (PETawatt Aquitaine Laser) facility. We evidence that by dividing the beam into small subapertures fitting the available grating size, the sub-beam can be individually compressed below 1 ps, synchronized below 50 fs and then coherently added thanks to a segmented mirror.

The Petawatt Aquitaine Laser (PETAL) facility was designed and constructed by the French Commissariat à l'énergie atomique et aux énergies alternatives (CEA) as an additional PW beamline to the Laser MegaJoule (LMJ) facility. PETAL energy is limited to 1 kJ at the beginning due to the damage threshold of the final optics. In this paper, we present the commissioning of the PW PETAL beamline. The first kJ shots in the amplifier section with a large spectrum front end, the alignment of the synthetic aperture compression stage and the initial demonstration of the 1.15 PW @ 850 J operations in the compression stage are detailed. Issues encountered relating to damage to optics are also addressed.

A multi-Petawatt high-energy laser PETAL coupled to the Ligne d'Intégration Laser (LIL) is under construction in the Aquitaine Region in France. This Petawatt laser will be dedicated to academic experiments in the fields of high energy density physics and ultra high intensity. Nd : glass laser chain coupled with the chirped pulse amplification (CPA technique allows delivery of high energy. Optical parametric CPA for pre-amplification and a new compression scheme will be implemented. PETAL is designed to deliver 3.6 kJ of energy in 500 fs on a target corresponding to 7.2 PW. The PETAL beam linked to the up to 60 kJ ns UV beams from the LIL will present new scientific research opportunities.