A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 μm/sup 2/ SRAM cell

Abstract

A leading edge 90 nm technology with 1.2 nm physical gate oxide, SO nm gate length, strained silicon, NiSi, 7 layers of Cu interconnects, and low k CDO for high performance dense logic is presented. Strained silicon is used to increase saturated NMOS and PMOS drive currents by 10-20% and mobility by > 50%. Aggressive design rules and unlanded contacts offer a l.0pm2 6-T S R A M cell using 193nm lithography. IntroductionThe power dissipation of modern microprocessors has been rapidly increasing, driven by increasing transistor count and clock frequencies. The rapidly increasing power has occurred even though the power per gate switching transition has decreased approximately (0.7)' per technology node due to voltage scaling and device area scaling. Figure 1 shows these trends for Intel's microprocessors and CMOS logic technology generations. In this paper we describe a 90 nm generation technology designed for high speed and low power operation. Strained silicon channel transistors are used to obtain the desired performance at 1.0V to 1.2V operation. renw 5 B 0 n 1 0 0 0 0~ Pentiud U) E 1.5 1 0.8 0.6 0.35 0.25 0.18 0.13 Technology (pm) Figure 1: Power and transistor switching energy trends. procesS Flow and Technology FeaturesFront-end technology features include shallow trench isolation, retrograde wells, shallow abrupt sourceldrain extensions, halo implants, deep sourcddrain, and nickel salicidation. N-wells and P-wells are formed with deep phosphw rous and shallow arsenic implants, and boron implants respectively. The trench isolation is 400 nm deep to provide robust inma-and inter-well isolation for N+ to P+ spacing below 240 nm while maintaining low junction capacitance. Sidewall spacers are formed with CVD Si,N4 deposition, followed by etch-back. Shallow sourcedrain extension regions are formed with arsenic for NMOS and boron for PMOS. Nisi is formed on poly-silicon gate and source-drain regions to provide low contact resistance.

Tip-enhanced Raman spectroscopy: principles and applications

“…Because the spatial fluctuations of strain can be deleterious for the performance of silicon devices, the nanoscale probing of strain in silicon has stimulated significant interest [63][64][65][69][70][71]. Introduction of strain in silicon using a SiGe buffer layer is a wellknown technique to enhance carrier mobility [73], which was used by Intel for the first time in the 90 nm process technology [74]. The strain-induced shift of the first order 520 cm -1 Raman peak associated with optical phonons in silicon has been used to spatially map stress variations using TERS, with a lateral resolution of 20-25 nm [11,70].…”

Black phosphorus nanoelectromechanical resonators vibrating at very high frequencies

“…19,20,21,22,23 For example, with a 2D tension (in N/m, as in surface tension) of 0.1nN/nm, single layer MoS 2 can be stretched by 0.05%, 24 corresponding to a bandgap modulation of 3.7meV; 25 while a 0.45% strain can be induced in black P by the same tension (in the armchair direction), 15 which leads to a 36.4meV bandgap widening, 23 one order of magnitude greater than that in MoS 2 . Such capability shall enable new nanoelectromechanical systems (NEMS) in which the electronic and optoelectronic properties of the nanomaterial could be efficiently tuned by the device strain, 26 thus may enable new black P devices in categories where currently only conventional materials are utilized, such as strained-channel FETs 27 and frequency-shift-based resonant infrared sensors. 28 To date, however, the exploration and implementation of black P mechanical devices have not yet been reported; such efforts have been plagued by the relative chemical activeness of black P:8 , 9 it can be readily oxidized in air, and the multiple processing steps (many involving wet chemistry) required in fabricating mechanical devices from layered 2D materials (lithography, metallization, etching and suspension, etc.)…”

Contribution of f- and g- transitions to electron intervalley scattering of n-S at temperatures 300 to 450 K

“…As known, «Intel Corporation» introduced n-MOS transistors with silicon uniaxially deformed in the direction [001] channels, thus improving the mobility of electrons around twice at T = 300K [1,2]. This increase is due to removal of intervalley scattering related with ftransitions, thereby increasing the steepness of the current-voltage characteristics (CVC) and cutoff frequency of switching.…”