The development of a mixed-signal test bus infrastructure -IEEE P1149.4 -as now in the final stages of the standardization process. Evaluating the test capabilities enabled by this infrastructure is an important step needed to support it as a well establ'ished standard. This paper presents experiments carried out with a tesl chip provided by the P1149.4 working group, which eaplore the architecture of the proposed analog boundary module to implement alternative testing methods. These include a method for parametric testing of passive components based on the monitoring of the power supply current, and a mixed current/voltage technique alloruing the implementation of correlation for testing analog and mixed-signal macros. INTERNATIONAL TEST CONFERENCE 0-78034209-7/97 $1 0.00 0 1997 IEEE Paper 21.3

This paper describes the design of a processor specific for testing cores embedded in system-on-chip. This processor, which can be implemented within a system's reconfigurable area, shall be responsible for scheduling and control test operations and perform preliminary data processing, as well as to provide the interface with an external tester. Building these test operations on-chip allows for simplifying external tester interface and to reduce testing time. The testing procedure and the infrastructure required to test an A/D converter is described as an example.