The trend toward finer pitch and higher performance integrated circuit devices has driven the semiconductor industry to incorporate copper and low-k dielectric materials. However, the low-k materials have lower modulus and poorer adhesion compared to the common dielectric materials. Thus, thermomechanical failure is one of the major bottlenecks in the development of Cu/low-k larger-die flip chip packages. This paper describes the optimization of the structural design of Chartered's C65 nm 21 mm × 21 mm die size flip-chip ball grid array package incorporated with fully active and functional ninemetal Cu/low-k layers and 150 μm interconnect pitch. The lowk material used in this paper is nonporous SiCOH with a k value of 2.9. A parametric study using 2-D plane strain finite element analysis was performed to study the effect of various parameters on the reliability of the large-die package in order to arrive at an optimized design. In order to have a simple criterion to predict the reliability of the yet-to-be-built largedie package, reliability tests were carried out on some existing 15 mm × 15 mm die Cu/low-k flip chip packages which were identical to the 21 mm × 21 mm die package except for the size. The packages were found to pass the reliability tests. 2-D plane strain finite element analyses were then performed on the 15 mm × 15 mm die. The computed delamination stresses at the low-k layer and the strain energy density dissipation per cycle in the critical solder ( W) were then used as a benchmark for the design of a larger flip chip package. The efficacy of the polymer encapsulated dicing lane technology was established. In this paper, the effect of the number of fluorosilicate glass layers, die thickness, substrate thickness, Cu post height, and underfill type on the delamination stresses in the low-k layer and W were determined. Specimens of the optimized large-die package were then fabricated and subjected to reliability tests. They were all found to pass the reliability tests. From these reliability tests, new benchmark values of the delamination stresses at the low-k layer and W are obtained, which can be used to aid in the design of large-die Cu/low-k flip chip packages.Index Terms-65 nm Cu/low-k, finite element analysis, flip chip package, large-die, solder joint reliability.

The trend toward finer pitch and higher performance integrated circuits (ICs) devices has driven the semiconductor industry to incorporate copper and low-k dielectric materials. However, the low-k materials have lower modulus and poorer adhesion compared to the common dielectric materials. Thus, thermo-mechanical failure is one of the major bottlenecks for development of a Cu/low-k larger die flip chip package. Very low modulus underfills must also be avoided because low modulus underfills transfer too much stress to the bumps which result in bump cracking in TC testing. A 2D plane strain analysis was performed to investigate the reliability of Chartered's C65nm 2lx2lmm 9metal Cu/ low-k, chips with 150um interconnect pitch in a FCBGA package. A series of parametric studies are performed by using Polymer Encapsulated Dicing Lane Technology (PEDL) to reduce 1 layer of FSG, variation of Cu post height, die thickness, substrate thickness, and underfill selection. The results obtained from the reduction of the stress in the low-k structure and the inelastic energy in the solder bumps modeling is useful to formulate design guidelines for packaging of large dies.

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