SiC nanowires were grown on monocrystalline 4H-SiC wafers by chemical vapor deposition using the vapor-liquid-solid growth mode. The growth direction of the nanowires was dictated by the crystallographic orientation of the 4H-SiC substrates. Two distinct types of nanowires were obtained. The first type crystallized in the 3C polytype with the AE111ae nanowire axes. These nanowires grew at 20°with respect to the substrate c-planes and exhibited high densities of stacking faults on those {111} planes that are parallel to the substrate c-planes. The second type featured the 4H structure albeit with a strong stacking disorder. The stacking faults in these nanowires were perpendicular to the [0001] nanowire axes. Possible growth mechanisms that led to the formation of 3C and 4H polytypes are discussed.

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A custom multi-chip power module packaging was designed to exploit the electrical and thermal performance potential of silicon carbide MOSFETs and JBS diodes. The dual thermo-mechanical package design was based on an aggressive 200°C ambient environmental requirement and 1200 V blocking and 100 A conduction ratings. A novel baseplate-free module design minimizes thermal impedance and the associated device junction temperature rise. In addition, the design incorporates a free-floating substrate configuration to minimize thermal expansion coefficient induced stresses between the substrate and case. Details of the module design and materials selection process will be discussed in addition to highlighting deficiencies in current packaging materials technologies when attempting to achieve high thermal cycle life reliability over an extended temperature range.

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