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A new polycrystalline silicon-germanium gate CMOS process has been developed for a submicron CMOS technology. The incorporation of germanium into a heavilydoped p-type polycrystalline-silicon (P+ poly-Si) gate material causes the gate workfunction to be reduced (more than 300 mV for a 60% Ge material), so that both NMOS and PMOS surfacechannel devices may be achieved. In addition, it improves the gate sheet resistance by increasing dopant activation. Whereas pure Ge is not suitable for use as a gate material due to its low melting point and its lack of a stable oxide, poly-Si 1 -,Ge, films with Ge mole fractions up to 0.6 were found to be completely compatible with standard VLSI fabrication processes, in regard to deposition and patterning techniques, high-temperature chemical and mechanical stability, and electrical stability and uniformity.

A new process for the fabrication of ion-sensitive fieldeffect transistors (ISFET's) together with CMOS circuits on the same chip is reported. The process is based on a standard 2-pm, n-well, CMOS process, which is only modified starting at the metal interconnect step. The interconnect layer used is tungsten silicide. ISFET's are fabricated with floating polysilicon gates, which are exposed by photolithographic masking and HF etching before silicon nitride is deposited on the wafer. This layer of Si3N4 acts both as the pH-sensitive insulator for the ISFET's and as a protection layer for the on-chip circuitry buried beneath it. Devices made with this process have a good p H sensitivity. Due to the floating polysilicon gate, these sensors do not have the sensitivity to ambient light which is a problem for conventional ISFET's. A sourcefollower circuit is described which provides an output voltage dependent on the threshold-voltage variations of the sensing transistor.

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