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With materials innovation driving recent logic and memory scaling in the semiconductor industry, High-Productivity Combinatorial™ (HPC) technology can be a powerful tool for finding optimum materials solutions in a cost-effective and efficient manner. This paper will review unique HPC wet processing, physical vapor deposition (PVD), and atomic layer deposition (ALD) capabilities that were developed, enabling site-isolated testing of multiple process conditions on a single wafer. These capabilities were utilized to generate workflows for exploration of new chalcogenide alloys for phase change memory, and for high-K dielectric metal gate effective work-function measurements for CMOS.

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Interfacial reactions of Ta with a Si–O–C low-dielectric constant (low-k) material and Cu/Ta/Si–O–C multilayers are investigated using x-ray photoelectron spectroscopy (XPS) and cross-sectional transmission electron microscopy (TEM). Data indicate that Ta deposition on the low-k substrate results in the initial formation of Ta oxide and TaC. Subsequent deposition of Ta eventually results in the formation of a metallic Ta overlayer at 300 K. The thickness of the initial Ta oxide/TaC-containing layer varies with the Ta deposition rate. At a deposition rate of ∼1 Å min−1, no metallic Ta is observed, even after 32 min sputter deposition time. In contrast, a film of roughly the same thickness, obtained after 15 s deposition at a rate of ∼2 Å s−1, is predominantly metallic Ta. Sputter deposition rates, derived from XPS data, are in agreement with film thicknesses derived from cross-sectional TEM data. Heating of Ta/low-k films in UHV results in no significant changes (as detected by XPS) up to 800 K. Cu deposited by sputter deposition onto a low-k surface covered with metallic Ta exhibits conformal growth, whereas 3d islanding is observed on a surface where TaC and Ta oxide are present. Cu diffusion into the bulk substrate is not observed at temperatures below 800 K in UHV.