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As scaling becomes increasingly difficult, 3D integration has emerged as a viable alternative to achieve the requisite bandwidth and power efficiency challenges. However mechanical stress induced by the through silicon vias (TSV) is one of the key constraints in the 3D flow that must be controlled in order to preserve the integrity of front end devices. For the first time an extended and comprehensive study is given for the stress induced by single-and arrayed TSVs and its impact on both analog and digital FEOL devices and circuits. This work provides a complete experimental assessment and quantifies the stress distribution and its effect on front end devices. By using a combined experimental and theoretical approach we provide a framework that will enable stress aware design and the right definition of keep out zone and ultimately save valuable silicon area.

We report for the first time the demonstration of 3D integrated circuits obtained by die-to-die stacking using Cu Through Silicon Vias (TSV). The Cu TSV process is inserted between contact and M1 of our reference 0.13µm CMOS process on 200mm wafers. The top die is thinned down to 25µm and bonded to the landing wafer by Cu-Cu thermo-compression. Both top and landing wafers contain CMOS finished at M2 to evaluate the process impact both FEOL and BEOL. The results confirm no degradation of the FEOL performance. The functionality of various ring oscillator topologies that include inverters distributed over both top and bottom dies connected through TSVs demonstrates excellent chip integrity after the TSV and 3D stacking process. 3D-SIC processRecently 3D integration has gained a lot of interest due to its potential to alleviate some important performance limitations facing CMOS scaling and because it enables so-called heterogeneous integration [1][2]. Different approaches to 3D integration are reported depending on system level requirements [3]. Our 3D Stacked IC (3D-SIC) process [4][5] uses IC foundry infrastructure to create Through Silicon Vias (TSVs) prior to BEOL processing. The main advantage of this approach is the fact that it has minimal impact on both FEOL and BEOL design and processing. Furthermore it offers very high TSV densities. The TSV process sequence is summarized in Fig. 1. Figure 1: Schematic of the 3D-SIC Through Silicon Via (TSV) module.After processing of the CMOS FEOL and the PMD stack, we patterned TSVs with a diameter of 5µm and a pitch of 10µm using a 3µm thick I-line resist. We performed an undercut free, resist-based TSV etch (Fig. 2); undercut underneath the contact layer is avoided by pre-deposition of a polymer on the sidewall of the etched PMD/STI stack prior to the Si etch. For electrical isolation, we deposit a 100nm SACVD O 3 -TEOS layer. The metallization sequence consists of applying a 80nm PVD Ta barrier and a 300nm PVD Cu seed followed by an ECD via fill using a 3-component plating chemistry. Finally the Cu overburden is polished in a top-side TSV CMP step (Fig. 3). After this process, we apply a standard, 2 metal layer BEOL process to finalize the top Si-die. Figure 2&3: FIB through TSV in vicinity of device after etch, strip& clean (left), and after TSV CMP and sintering (right). (Pt on top for contrast).After wafer test, the wafer is mounted on a temporary carrier and thinned down to a Si-thickness of ~25 m by a combination of grinding and CMP. In this process, the TSVs are exposed on the wafer backside. Next the Si is recessed by dry etching over a distance of ~700nm with respect to the copper TSV. In this work the dies were then stacked by Cu-Cu thermo-compression bonding in a Die-to-Die (D2D) fashion, although compatibility with Die-to-Wafer integration remains. Figure 4 shows an optical 3D reconstruction of the obtained 3D stack. Figure 4: Optical 3D reconstruction based on multiple images at different height of thinned top die stacked to a bottom die by Cu-Cu bonding.

In this paper, we investigate the electrical behavior of TSV with increasing temperatures (25-150 o C). TSV capacitance, leakage current and TSV resistance with varying temperatures are reported. TSV C-V characteristics are analyzed to extract the oxide charges. It is confirmed that the depletion behavior of TSV can be exploited to reduce TSV capacitance even at higher temperatures. In addition, lumped RC model of the TSV for circuit simulations is enhanced by incorporating measured TSV resistance and capacitance change due to temperature. The results are corroborated with the 2D/3D Ring Oscillator (RO) measurements at different temperatures. IntroductionThree-dimensional (3-D) ICs are promising to keep pace with Moore's law in the forthcoming decade. In addition to FEOL transistors and BEOL interconnects, Through Silicon Via (TSV) forms an integral component of 3-D ICs. Functional 3D circuits in 130nm technology obtained by a 3D stacked IC approach using both, TSV First and cost effective solution Die-to-Wafer Hybrid Collective bonding have already been demonstrated by IMEC [1][2][3][4][5]. The densely packed transistor arrays in contemporary 3-D ICs render higher operating temperatures [6]. Because of elevated temperatures the performance of 3-D circuit elements becomes increasingly important and hence require high temperature characterization of 3-D circuit elements.Various schemes to exploit the depletion behavior of the silicon substrate to reduce the TSV capacitance have already been reported [7]. The depletion behavior of silicon can also be exploited by tailoring the oxide charges during the TSV process [8]. But, it remains to be seen if the depletion behavior of silicon could still be exploited at elevated operating temperatures or not. Hence, the effect of temperature on the TSV C-V characteristics is of increasing interest. This paper focuses on the high temperature characterization of TSV capacitance, leakage and resistance. High temperature performance of 2D/3D ROs is also analyzed and is correlated to the rise of TSV capacitance at higher temperatures.

Imaging in the infrared wavelength range has been fundamental in scientific, military and surveillance applications. Currently, it is a crucial enabler of new industries such as autonomous mobility (for obstacle detection), augmented reality (for eye tracking) and biometrics. Ubiquitous deployment of infrared cameras (on a scale similar to visible cameras) is however prevented by high manufacturing cost and low resolution related to the need of using image sensors based on flip-chip hybridization. One way to enable monolithic integration is by replacing expensive, small-scale III–V-based detector chips with narrow bandgap thin-films compatible with 8- and 12-inch full-wafer processing. This work describes a CMOS-compatible pixel stack based on lead sulfide quantum dots (PbS QD) with tunable absorption peak. Photodiode with a 150-nm thick absorber in an inverted architecture shows dark current of 10−6 A/cm2 at −2 V reverse bias and EQE above 20% at 1440 nm wavelength. Optical modeling for top illumination architecture can improve the contact transparency to 70%. Additional cooling (193 K) can improve the sensitivity to 60 dB. This stack can be integrated on a CMOS ROIC, enabling order-of-magnitude cost reduction for infrared sensors.