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Modern wireline transceivers are explored to understand the limitations in their design and how their performance-in terms of speed and power consumptioncan be pushed. This exploration leads to the revelation that charge-steering based transceivers have a high potential. As such, an in-depth transient analysis of the basic charge-steering latch is presented, providing new insight into the operation of chargesteering circuits. This insight is utilized to develop design equations for the basic charge-steering latch. The design equations lead to improvement in charge-steering latch design (lower power consumption, higher swing) when compared to prior art. While prior art focused on charge-steering systems (ie. data converters and SerDes), the focus on individual latch improvement could also improve these systems. Several new charge-steering latch topologies are also proposed. The transient analysis is extended to one of these latches, the charge-steering latch with a clocked cross-coupled pair. New design equations are also presented for this latch. Post-layout simulations of these latches are done in 28nm FD-SOI CMOS and further simulations are performed in 65nm CMOS. The new design equations and latch topologies enable the use of charge-steering latches at 28Gb/s and beyond, at new levels of performance. Power savings of as much as 40% are demonstrated by the new topologies, all other specifications being equal. As data transmission speeds are pushed to as much as 1 terabit per second, single lane transceivers are required which operate at 56Gb/s and beyond. The new charge-steering circuits and design equations can enable a 56Gb/s transceiver when used in a half-rate architecture. ii First, I would like to acknowledge Dr. Calvin Plett for his supervision of my thesis. His willingness to supervise me almost a year after I started my Masters is very much so appreciated and his expertise of integrated circuits has been extremely valuable in the completion of my thesis. I also appreciate his facilitating my relationship with Ciena Corporation where I had the opportunity to learn from many other experts in integrated circuit design. My manager at Ciena, Dr. Naim Ben-Hamida, has been very graceful in lending me his time, as have others on the Analog Integrated Circuit team, including Dr. Jerry Lam and Dr. Sadok Aouini. But a special thanks must go to Dr. Mahdi Parvizi. He deserves as much credit as anyone for this thesis. Not only did he point me in the initial direction of researching charge-steering circuits but he has spent countless hours looking at these circuits with me and giving me new ideas. I could not have completed this thesis without his help. Many others at Ciena also deserve acknowledgment; Mouadh Abidi and Tigran Zohrabyan for their advice on layout and the other graduate students here, Matthew Mikkelson and Alex Jiang, for welcoming me into Ciena. I look forward to continuing my research with all of the above listed. I must also acknowledge David Berton, who was instrumental in helping me through gradua...