Design and implementation of signal processing and synchronization algorithms for digital receivers are challenging tasks, especially concerning the verification phase that must cover as many functional tests as possible. This paper discloses the entire internal architecture of the receive chain of the ETSI DVB-S2 digital satellite communication standard and the methodology used for implementing it. It covers architectural, algorithm, and RTL design, together with laboratory set-up, FPGA prototyping and VLSI resource estimation in 65nm CMOS. The result section demonstrates that our approach is able to synchronize and demodulate an 8-PSK DVB-S2 compliant signal, corrupted by all the impairments expected in a digital receiver.
The generation of an optimized factory layout is a central element of the factory planning process. The generated factory layout predefines multiple characteristics of the future factory, such as the operational costs and proper resource allocations. However, manual layout planning is often time and resource-consuming and involves creative processes. In order to reduce the manual planning effort, automated, computer-aided planning approaches can support the factory planner to deal with this complexity by generating valuable solutions in the early phase of factory layout planning. Novel approaches have introduced Reinforcement Learning based planning schemes to generate optimized factory layouts. However, the existing research mainly focuses on the technical feasibility and does not highlight how a Reinforcement Learning based planning approach can be integrated into the factory planning process. Furthermore, it is unclear which information is required for its application. This paper addresses this research gap by presenting a holistic framework for Reinforcement Learning based factory layout planning that can be applied at the initial planning (greenfield planning) stages as well as in the restructuring (brownfield planning) of a factory layout. The framework consists of five steps: the initialization of the layout planning problem, the initialization of the algorithm, the execution of multiple training sets, the evaluation of the training results, and a final manual planning step for a selected layout variant. Each step consists of multiple sub-steps that are interlinked by an information flow. The framework describes the necessary and optional information for each sub-step and further provides guidance for future developments.
This paper presents the design of a BCH Decoder for digital satellite TV Communications. It includes an architecture design specification, as well as the results of FPGA prototyping and of the logical and physical synthesis in 65nm CMOS. Moreover, it can be used as a basis for BCH Decoder designs for other kind of communications or even storage error correction.
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