For monolithic heterogeneous integration, fast yet low-power processing and storage, and high integration density, the objective of the ED GREAT project is to co-integrate multiple digital and analog functions together within CMOS by adapting the Magnetic Tunneling Junctions (MTJ s) into a single baseline technology enabling logic, memory, and analog functions, particularly for Internet of Things (loT) platforms. This will lead to a unique STT-MTJ cell technology called Multifunctional Standardized Stack (MSS). This paper presents the progress in the project from the technology, compact modeling, process design kit, standard cells, as well as memory and system level design evaluation and exploration. The proposed technology and toolsets are giant leaps towards heterogeneous integrated technology and architectures for loT.

To tackle the key issues of monolithic heterogeneous integration, fast yet low power processing, high integration density, fast yet low power storage, the goal of the GREAT project is to co-integrate multiple functions like sensors ("Sensing"), RF receivers ("Communicating") and logic/memory ("Processing/Storing") together within CMOS by adapting the STT-MTJs (Magnetic devices) to a single baseline technology enabling logic, memory, and analog functions in the same System-on-Chip (SoC) as the enabling technology platform for Internet of Things (IoT). This will lead to a unique STT-MTJ cell technology called Multifunctional Standardized Stack (MSS). The major outputs of GREAT are the technology and the architecture platform for IoT SoCs providing better integration of embedded & mobile communication systems and a significant decrease of their power consumption. Based on the STT-MTJs (now viewed as the most suitable technology for digital applications and with a huge potential for analog subsystems) unique set of performances (non-volatility, high speed, infinite endurance and moderate read/write power), GREAT will achieve the same goal as heterogeneous integration of devices but in a much simpler way since the MSS will enable different functions using the same technology.

Phone: þ33 4 93 95 42 00, Fax: þ33 4 93 95 83 61The present work is dedicated to the study of the influence of metal-organic vapor phase epitaxy (MOVPE) growth conditions on the properties of AlGaN/GaN high electron mobility transistor (HEMT) heterostructures with thin simple buffer layers on Si(111). In a first series of samples grown on high resistivity silicon, the conditions were varied within the GaN buffer layer while kept unchanged for the AlN nucleation layer and HEMT barrier and cap layers. XRD and AFM revealed some differences in epilayers structural quality especially in case of excessive growth pressure or V/III ratio. Capacitancevoltage (CV) measurements revealed differences in the pinchoff regime of the two-dimensional electron gas (2DEG) located at the AlN/GaN interface. Except in one case, the buffer leakage current between isolated devices correlates with the pinch-off behavior. The majority of these structures exhibited sheet carrier densities of 1 Â 10 13 cm À2 and electron mobility between 1100 and 1400 cm 2 V À1 s À1 depending on the GaN channel growth conditions. The output and transfer characteristics (maximum drain currents and leakage currents) of the transistors are in agreement with the previous electrical characterizations. Thanks to the combination of structural and electrical characterizations we are then able to determine the optimized growth conditions for such HEMT structures. Compared with high resistivity silicon, we obtained better structural and electrical quality on conductive substrates. A 2DEG with an electron mobility of 1700 cm 2 V À1 s À1 has been achieved within a structure with a 0.5 mm thick buffer producing an off-state breakdown voltage of 117 V. This reveals the crucial role of the substrate surface properties on the resulting quality of the heterostructures.