In this paper, we examine the feasibility of fully integrated voltage regulator for the power-optimized system-on-chip (SoC). The challenges and tradeoffs in designing fullyintegrated buck switching regulators in CMOS process are described and a compact macro-power-model of a regulator is created. Optimization using geometric programming finds the optimal active and passive device sizes of on-chip regulator for highest efficiency in current and future process technologies. A fully-integrated switching regulator is designed and fabricated in a 0.35-pm CMOS process to validate our modeling. The model is extrapolated to emerging CMOS technologies to show that >70% efficiency is possible. Power-Supply Regularor," IEEEJoumnal o/ Solid Store Circuils, April 1999, pp. 520-528. 141 ASITIC; Analysis and Simulation of Inductors and Transformen for ..

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