In order to evaluate and validate the latest trends of power-hardware-in-loop (PHIL) test setup, the dc-dc buck converter is modelled within a real-time system where the simulation model of the converter is exported to FPGA NI PXIe with a time step of 250 ns. PHIL setup allows high flexibility, the benefit of graphical programming, and advanced investigation of the control system for a converter without any safety concern and with the possibility of testing against situations that rarely occur in the field. The LabVIEW-FPGA has been used as a prototyping environment for a digital controller with the help of OPAL-RT eHS software and NI hardware. Such collaboration enables other software such as MATLAB/Simulink, Multisim, PLECS, PSIM, and LabVIEW Co-simulation for accelerating innovative research and development. This research work presents a more efficient and effectual NI PXIE platform with at least ten times more FPGA capability. This paper highlights the hardware-software toolset's performance and the proposed methodology by addressing regulation issues in dc-dc converters. For more satisfactory and reliable operation real-time simulation study of a dc-dc buck converter is evaluated at different parametric variations under the closed-loop PI controller. Finally, the executed model's effectiveness for a closed loop buck converter with real DC loads is validated through the hardware-in-loop (HIL) laboratory setup.

Modular multilevel converter (MMC) is a proven technology for HVDC applications due to its salient features such as modularity and excellent power quality. To ensure best possible grid support, recent grid codes require incorporating fault ride-through (FRT) strategies so that HVDC converter stations remain connected and maintain reliable operation under various symmetrical and asymmetrical AC faults. In this paper, a communication-free enhanced fault ride-through technique without the need of DC chopper has been proposed. The proposed FRT strategy ensures quick post fault recovery operation and can effectively manage DC link and capacitor voltages within safe limits. Along with proposed FRT strategy, in order to avoid high circulating current (CC) inside an MMC, this paper has proposed an optimal circulating current control approach based on proportional resonant and PI controllers in an abc reference frame. The suggested technique lowers the ripple in capacitor voltages while reducing the magnitude of the CC. Under both balanced and unbalanced ac grid conditions, the ripple in the dc link voltage is also reduced without the use of dual synchronous reference frame or any additional controllers. Simulation results confirm the effectiveness of the proposed FRT and CC suppression techniques for a 580-kV, 850-MW MMC-based HVDC system.