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A substantially large class of programs operate in distributed and real-time environments, and an integral part of their correctness specification requires the expression of time-critical properties that relate the occurrence of events of the system. We focus on the formal specification and reasoning about the correctness of such programs. We propose a system of temporal logic, RTCTL (Real-Time Computation Tree Logic), that allows the melding of qualitative temporal assertions together with real-time constraints to permit specification and reasoning at the twin levels of abstraction: qualitative and quantitative. We show that several practically useful correctness properties of temporal systems, which need to express timing as an essential part of their functionality requirements, can be expressed in RTCTL. We also develop a model-checking algorithm for RTCTL whose complexity is linear in the size of the RTCTL specification formula and in the size of the global state-space graph. Finally, we present an optimal, exponential time tableau-based decision procedure for the satisfiability of RTCTL formulae, which can be used as the basis of a technique to automate the synthesis of real-time programs from specifications. I n t r o d u c t i o nMotivated mainly by the virtue of separating concerns, most of the research into the formal specification and reasoning about the correctness of programs has paid little heed to dealing with quantitative temporal properties. In fact, this has proved to be an advantageous abstraction because, in many applications, the correctness properties of a program need to be stated independently of concerns of efficiency, performance, or features (e.g., the speed) of the underlying hardware implementation. Given this, a common characteristic of most temporal or modal logics heretofore proposed for program reasoning (cf.

This paper introduces time window temporal logic (TWTL), a rich expressivity language for describing various time bounded specifications. In particular, the syntax and semantics of TWTL enable the compact representation of serial tasks, which are typically seen in robotics and control applications. This paper also discusses the relaxation of TWTL formulae with respect to deadlines of tasks. Efficient automata-based frameworks to solve synthesis, verification and learning problems are also presented. The key ingredient to the presented solution is an algorithm to translate a TWTL formula to an annotated finite state automaton that encodes all possible temporal relaxations of the specification. Case studies illustrating the expressivity of the logic and the proposed algorithms are included.

There has been much interest in decision procedures for testing satisfiability of formulas in various systems of temporal logic. This is due to the potential applications of such decision procedures to the mechanical synthesis of concurrent programs from their specifications.However, formulae of classical temporal logics can express specifications of only a fixed number of processes. Thus, their use in mechanical synthesis suffers from two limitations, viz., the state explosion problem and their inability to describe dynamic systems, ones in which the number of processes could vary to adapt to external demands. In this paper, we present an indexed temporal logic, Indexed Simplified Computation Tree Logic (Indexed SCTL), that can be used to specify programs with arbitrarily many similar processes. With a view to synthesizing such programs mechanically from specifications, we pose two new decision problems: almost always satisfiability and almost always unsatisfiability. We show that both these problems are decidable for Indexed SCTL, and, in fact, that every Indexed SCTL specification is either almost always satisfiable, i.e., it can be realized by a concurrent program provided that the number of constituent processes exceeds a certain value that depends on the specification (and is determined by our decision procedure), or is almost always unsatisfiable,i.e., no concurrent program with more than a certain number (which, again, is determined by the decision procedure) of processes can ever realize the specification. Finally, we show how our results could be used to automate the synthesis of a concurrent system that meets a desired Indexed SCTL specification which is almost always satisfiable.