In a standard industrial approach the timing performance verification is obtained using a tabular method that necessitates a great amount of simulations. They must specify, for each drive in each logic family: the load, the input slope, the temperature and the supply voltage sensitivity, for each edge, of the transition time and propagation delay. Extending a logical effort like based model of timing performance of CMOS structures we show in this paper that it is possible to define-a specific performance representation allowing a continuous representation of the performance sensitivity of a complete family. We describe the parameter calibration procedure and validate the proposed representation on a 0.13pm process by comparing the performance sensitivity deduced from this representation to sensitivity values obtained from electrical simulations performed with the full process model of the foundry.

Abstruct-The paper describes the mechanical and electrical contact properties of a typical fired wedge-connector. The measured forces and displacements in the connector components are compared with the predictions of a finite element analysis (FEA) of a wedge-connector interfaced with solid aluminum conductors. The distribution of mechanical stresses resulting from typical applied mechanical loads are evaluated using a nonlinear FEA code. The nonlinear input data for the FEA calculations were obtained from mechanical testing of metal specimens obtained from connectors used in the investigation. Measurements of contact resistance of the electrical interfaces are also reported. The wipe-off of surface oxide films from the electrical interfaces during connector installation is described.

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