Synchronization is an important issue in modern system design as systems-on-chips integrate more diverse technologies, operating voltages, and clock frequencies on a single substrate. This paper presents a methodology for the design and implementation of a self-timed reconfigurable control device suitable for a parallel cascaded flip-flop synchronizer based on a principle known as wagging, through the application of distributed feedback graphs. By modifying the endpoint adjacency of a common behavior graph via one-hot codes, several configurable modes can be implemented in a single design specification, thereby facilitating direct control over the synchronization time and the mean-time between failures of the parallel master-slave latches in the synchronizer. Therefore, the resulting implementation is resistant to process nonidealities, which are present in physical design layouts. This paper includes a discussion of the reconfiguration protocol, and implementations of both a sequential token ring control device, and an interrupt subsystem necessary for reconfiguration, all simulated in UMC 90-nm technology. The interrupt subsystem demonstrates operating frequencies between 505 and 818 MHz per module, with average power consumptions between 70.7 and 90.0 µW in the typical-typical case under a corner analysis.

Synchronization via wagging is a method by which a high bandwidth data signal can be partitioned into several lower bandwidth data signals in order to increase the synchronization time of a master-slave latch configuration, and by consequence the mean time between failure for each of the latches in the lower bandwidth array of devices. Furthermore, reconfigurable controller hardware grants the circuit designer direct control over the synchronization time of the array of master-slave latches via the use of one-hot control codes.This work assesses the benefits of unified reconfigurable controller designs over brute force methods when accounting for effects such as process variations. The reconfiguration protocol is discussed, and three separate controller implementations for a wagging synchronizer are compared in a UMC 90 nm technology with operational frequencies of 37 GHz, 19 GHz, and 12 GHz and average power consumption between 1.3 μW and 7.5 μW per cell in the typical case. Furthermore, the area cost of a unified reconfigurable control device is shown to have a linear growth in complexity as compared the exponential growth present when utilizing selective hardware replication of configurable modes. Conclusions are then drawn outlining future directions for research.