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Although traffic safety continues to improve overall, fatalities of vulnerable traffic participants and pedal cyclists specifically have reached 30-year highs. While automotive radar sensors continue to advance and are integrated in more and more vehicles, they are not ideally suited to detect pedal cyclists, especially in complicated traffic scenarios. To mitigate the problem of the lower radar-cross section (RCS) of the cyclist, equipping them with harmonic radio frequency identification (RFID) tags is proposed. The presented system showcases the benefits of this approach by being able to conduct conventional automotive radar measurements and detect tags simultaneously. In this work, we present the printed-circuit boards (PCBs) and the necessary chipset, while especially focusing on the design of a power-efficient harmonic RFID tag. By improving the gain per current of an amplifier chain, the tag enables a range sufficient for urban scenarios while consuming little enough current to be powered by battery-operated lights. This enables the detection of pedal cyclists even in complicated scenarios at a distance of up to 80 m.

This paper presents SiGe-based transmitter and receiver chips for a radio frequency identification (RFID) frontend in the 61-GHz industrial, scientific, and medical (ISM) frequency band. The chips are fabricated in a modern 130-nm SiGe BiCMOS technology with HBTs offering an f T of 250 GHz and f max of 370 GHz. The presented transmitter consists of a fundamental voltage-controlled oscillator (VCO), a power amplifier (PA), lumped element Wilkinson power dividers, and a static divide-by-16 chain for stabilization within a phase-locked loop (PLL). Two variants of the transmitter are fabricated with supply voltages of 3.3 and 5 V, respectively. The transmitters are designed to provide an efficient signal source to supply a passive RFID tag with the maximum allowed 20-dBm effective isotropic radiated power (EIRP) for short-range devices. The 3.3-V transmitter chip achieves a peak output power of 17 dBm, PAE PA of 18.6% and dc-to-RF efficiency of 12.9% (excluding the divider). At 61 GHz, a phase noise of −102 dBc/Hz at 1 MHz offset is achieved. The power consumption for the 5-and 3.3-V transmitter chips is 710 and 482 mW, respectively. The receiver chip is implemented as two Gilbert cell mixers inphase quadrature configuration to compensate for destructive interference that may be caused by varying distance between reader and tag.

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