The interface between a carbon nanotube (CNT) and its environment can dramatically affect the electrical properties of CNT-based field-effect transistors (FETs). For such devices, the channel environment plays a significant role inducing doping or charge traps giving rise to hysteresis in the transistor characteristics. Thereby the fabrication process strongly determines the extent of those effects and the final device performance. In CNT-based devices obtained from dispersions, a proper individualization of the nanotubes is mandatory. This is generally realized by an ultrasonic treatment combined with surfactant molecules, which enwrap nanotubes forming micelle aggregates. To minimize impact on device performance, it is of vital importance to consider post-deposition treatments for removal of surfactant molecules and other impurities. In this context, we investigated the effect of several wet chemical cleaning and thermal post treatments on the electrical characteristics as well as physical properties of more than 600 devices fabricated only by wafer-level compatible technologies. We observed that nitric acid and water treatments improved the maximum-current of devices. Additionally, we found that the ethanol treatment successfully lowered hysteresis in the transfer characteristics. The effect of the chemical cleaning procedures was found to be more significant on CNT-metal contacts than for the FET channels. Moreover, we investigated the effect of an additional thermal cleaning step under vacuum after the chemical cleaning, which had an exceptional impact on the hysteresis behavior including hysteresis reversal. The presence of surfactant molecules on CNT was evidenced by X-ray photoelectron and Raman spectroscopies. By identifying the role of surfactant molecules and assessing the enhancement of device performance as a direct consequence of several cleaning procedures, these results are important for the development of CNT-based electronics at the wafer-level.

Carbon nanotube (CNT)-based field-effect transistors have demonstrated great potential for high-frequency (HF) analog transceiver electronics. Despite significant advancements, one of the remaining challenges is the optimization of the device architecture for obtaining the highest possible speed and linearity. While most studies so far have concentrated on symmetrical top gated FET devices, we report on the impact of the device architecture on their HF performance. Based on a wafer-level nanotechnology platform and device simulations, transistors with a buried gate having different widths and positions in the FET channel have been fabricated. Analysis of several FETs with nonsymmetrical gate electrode location in the channel revealed a speed increase of up to 18% measured by the external transit frequency f T and maximum frequency of oscillation f max . Although only randomly oriented CNTs with a density of 25 CNTs/μm and 280 nm long channels were used in this study, transit frequencies up to 14 GHz were obtained.

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