This paper introduces a new technique for the measurement of the thermal resistance of HBTs. The method is very simple, because it requires only standard dc I C -V CE measurements taken at different baseplate temperatures, but it is able to account for the dependence of the thermal resistance on both the baseplate temperature and the dissipated power (under the simplifying assumption that the thermal resistance increases linearly with the dissipated power). We have obtained and shown consistent results extracted from devices with an emitter area ranging from 90 µm 2 (1 finger) to 1080 µm 2 (12 fingers). The thermal-resistance values extracted with a standard and wellknown technique are seen to fall inside the range of our results. We have also applied an alternative method that assumes a linear dependence between thermal resistance and junction temperature, and we have shown that both models lead to similar results, which points to the consistency and robustness of our extraction technique.

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The Si/SiO2 interface is attracting new interest as gate dielectrics in MOS devices become ultra thin. In this paper, the impact of pre-gate cleaning on the morphology of the Si/SiO2 interface and the electrical performance of CMOS gate oxides has been systematically investigated. Using the High-Resolution Transmission Electron Microscopy (HRTEM) technique, we observed the Si/SiO2 interface at an atomic level. We have found a direct experimental relationship between the pre-gate cleaning scheme, Si/SiO2 interface morphology, and the electrical properties of CMOS gate oxides. When the ratio of H2O2:NH4OH ≥ 1.45, the roughness of the Si/SiO2 interface was dramatically improved, which, in turn, increased the Charge-to-Breakdown to an ideal value.

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