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Securing thousands of connected, resourceconstrained computing devices is a major challenge nowadays. Adding to the challenge, third party service providers need regular access to the system. To ensure the integrity of the system and authenticity of the software vendor, secure boot is supported by several commercial processors. However, the existing solutions are either complex, or have been compromised by determined attackers. In this scenario, open-source secure computing architectures are poised to play an important role for designers and white hat attackers.In this manuscript, we propose a lightweight hardwarebased secure boot architecture. The architecture uses efficient implementation of Elliptic Curve Digital Signature Algorithm (ECDSA), Secure Hash Algorithm 3 (SHA3) hashing algorithm and Direct Memory Access (DMA). In addition, the architecture includes Key Management Unit, which incorporates an optimized Physical Unclonable Function (PUF) for providing keys to the security blocks of the System on Chip (SoC), among which, secure boot and remote attestation. We demonstrated the framework on RISC-V based SoC. Detailed analysis of performance and security for the platform is presented.

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The continuous quest for energy-efficient computing has led towards the adoption of fine-grained controls in processor sub-systems, of which power delivery network is the most prominent one. Recent industry trends reflect a shift towards on-chip, integrated voltage regulator (IVRs) to that effect. We undertake a thorough and quantitative evaluation of different power delivery networks for modern microprocessors. In contrast to the current trend, we conclude that IVR schemes perform worse compared to the conventional off-chip voltage regulator scheme. Further, we present studies on diverse workloads and Thermal Design Points (TDPs) to highlight the importance of workload-specific power delivery scheme. To the best of our knowledge, this is the first comprehensive study across processors' TDPs and workloads.