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The advanced process technologies have well known yield loss due to the degradation of pattern fidelity. The process to compensate for this problem is advanced resolution enhancement techniques (RET) and optical proximity correction (OPC). By design, the creation of RET/OPC recipes and the calibration of process models are done very early in the process development cycle with data that are not made of real designs since they are not yet available, but made of test structures that represent different sizes, distances and topologies. The process of improving the RET/OPC recipes and models is long and tedious, it is usually a key contributor to quick production ramp-up. It is very coverage limited by design. The authors will present a proposed system that, by design, is dynamic, and allows the RET/OPC production system to reach maturity faster through a detailed collection of hotspots identified at the design stage. The goal is to reduce the lapse of time required to get mature production RET/OPC recipes and models.

As technology nodes scale beyond 20nm node, design complexity increases and printability issues become more critical and hard for RET techniques to fix. It is now mandatory for designers to run lithography checks prior to tape out and acceptance by the foundry. As lithography compliance became a sign-off criterion, lithography hotspots are increasingly treated like DRC violations. In the case of lithography hotspot, layout edges that should be moved to fix the hotspot are not necessarily the edges directly touching it. As a result of that, providing the designer with a suggested layout movements to fix the lithography hotspot is becoming a necessity. Software solutions generating hints should be accurate and fast. In this paper we are presenting a methodology for providing hints to the designers to fix Litho-hotspots in the 20nm and beyond.

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