Motivated by the physics of strings and branes, we develop a class of Markov chain Monte Carlo (MCMC) algorithms involving extended objects. Starting from a collection of parallel Metropolis-Hastings (MH) samplers, we place them on an auxiliary grid, and couple them together via nearest neighbor interactions. This leads to a class of "suburban samplers" (i.e., spread out Metropolis). Coupling the samplers in this way modifies the mixing rate and speed of convergence for the Markov chain, and can in many cases allow a sampler to more easily overcome free energy barriers in a target distribution. We test these general theoretical considerations by performing several numerical experiments. For suburban samplers with a fluctuating grid topology, performance is strongly correlated with the average number of neighbors. Increasing the average number of neighbors above zero initially leads to an increase in performance, though there is a critical connectivity with effective dimension d eff ∼ 1, above which "groupthink" takes over, and the performance of the sampler declines.

Efficient hardware implementations of statistical inference continue to grow in importance for a wide range of computing applications. While CPU cycles are increasingly being used for statistical inference, transistors are also becoming increasingly statistical. For implementing statistical algorithms, could it be that statistical electronic substrates are a feature rather than a bug?We show that inference models can often be built from local constraints, and explain the gate-level mathematical functions required for the resulting inference solver. We suggest that signals should consist of probabilistic populations of particles representing samples from a probability distribution, with gate functions acting to transform these ensembles. Using this mapping from statistical physics to statistical inference, we present Bayesian logic circuits as highly efficient alternatives to digital standard cell libraries. For particular inference computations, novel VLSI architectures based on Bayesian logic circuits consume orders of magnitude less power and silicon area compared to conventional digital processors.

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