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We present measurements of silicon ͑Si͒ metal-oxide-semiconductor ͑MOS͒ nanostructures that are fabricated using a process that facilitates essentially arbitrary gate geometries. Stable Coulomb-blockade behavior showing single-period conductance oscillations that are consistent with a lithographically defined quantum dot is exhibited in several MOS quantum dots with an open-lateral quantum-dot geometry. Decreases in mobility and increases in charge defect densities ͑i.e., interface traps and fixed-oxide charge͒ are measured for critical process steps, and we correlate low disorder behavior with a quantitative defect density. This work provides quantitative guidance that has not been previously established about defect densities and their role in gated Si quantum dots. These devices make use of a double-layer gate stack in which many regions, including the critical gate oxide, were fabricated in a fully qualified complementary metal-oxide semiconductor facility.

Articles you may be interested inEffects of type of reactor, crystallinity of SiC, and N F 3 gas pressure on etching rate and smoothness of SiC surface using N F 3 gas plasma A process for achieving high yield of SiC through wafer via holes without trenching or micromasking and with excellent electrical connection after subsequent metal plating across full wafers was developed for use in high electron mobility transistors ͑HEMTs͒ and microwave monolithic integrated circuits ͑MMICs͒ using an inductively coupled plasma etch. Consideration was given to the choice of wafer platen, hard mask, gas chemistry, surface treatments, and plasma parameters in order to achieve an acceptable etch rate while at the same time minimizing trenching and micromasking that can harm via yield. In addition, the issue of wafer thickness variation and etch nonuniformity leading to punch through of Au pads at the bottom of the vias was addressed by the addition of a metal layer to the front side of the wafer. The etch rate achieved for 25% of a 2 in. diameter wafer is approximately 3800 Å / min while demonstrating acceptable levels of trenching and micromasking with little or no Au punch through. The final process has been demonstrated to achieve Ͼ95% yield across a full 2 in. diameter, 100 m thick wafer with a high density of vias.

Laterally coupled charge sensing of quantum dots is highly desirable, because it enables measurement even when conduction through the quantum dot itself is suppressed. In this work, we demonstrate such charge sensing in a double top gated MOS system. The current through a point contact constriction integrated near a quantum dot shows sharp 2% changes corresponding to charge transitions between the dot and a nearby lead. We extract the coupling capacitance between the charge sensor and the quantum dot, and we show that it agrees well with a 3D capacitance model of the integrated sensor and quantum dot system.

Using a two-step method of plasma and wet chemical etching, we demonstrate smooth, vertical facets for use in Al x Ga 1Àx N-based deep-ultraviolet laser-diode heterostructures where x = 0 to 0.5. Optimization of plasma-etching conditions included increasing both temperature and radiofrequency (RF) power to achieve a facet angle of 5 deg from vertical. Subsequent etching in AZ400K developer was investigated to reduce the facet surface roughness and improve facet verticality. The resulting combined processes produced improved facet sidewalls with an average angle of 0.7 deg from vertical and less than 2-nm root-mean-square (RMS) roughness, yielding an estimated reflectivity greater than 95% of that of a perfectly smooth and vertical facet.