Articles you may be interested inEffects of type of reactor, crystallinity of SiC, and N F 3 gas pressure on etching rate and smoothness of SiC surface using N F 3 gas plasma A process for achieving high yield of SiC through wafer via holes without trenching or micromasking and with excellent electrical connection after subsequent metal plating across full wafers was developed for use in high electron mobility transistors ͑HEMTs͒ and microwave monolithic integrated circuits ͑MMICs͒ using an inductively coupled plasma etch. Consideration was given to the choice of wafer platen, hard mask, gas chemistry, surface treatments, and plasma parameters in order to achieve an acceptable etch rate while at the same time minimizing trenching and micromasking that can harm via yield. In addition, the issue of wafer thickness variation and etch nonuniformity leading to punch through of Au pads at the bottom of the vias was addressed by the addition of a metal layer to the front side of the wafer. The etch rate achieved for 25% of a 2 in. diameter wafer is approximately 3800 Å / min while demonstrating acceptable levels of trenching and micromasking with little or no Au punch through. The final process has been demonstrated to achieve Ͼ95% yield across a full 2 in. diameter, 100 m thick wafer with a high density of vias.

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In 2013 Raytheon began to integrate deep submicron (≤0.25 µm gate) 200mm GaN on Si HEMT processes within a commercial CMOS Si Foundry environment. When fully realized, these processes will demonstrate multi GHz GaN on Si MMICs by leveraging a fully subtractively processed transistor coupled with multi level copper based back end of line (Cu BEOL) processes. This work provides a status update on the progress towards that goal.