This paper outlines yield improvements in the integration of damascene copper in low-k SiCOH intermetal dielectric at 65 nm dimensions. Large defect reductions were seen by RIE, wet cleans and CMP process optimization. RIE improvements led to reductions of thirty three percent for missing pattern defects while wet clean optimization resulted in more than a fifty percent reduction in metal voids. CMP carrier head changes provided a more corrosion resistant process and higher throughput. Additionally, a high performance M1 module that maintained process window for all sectors was developed.

A comprehensive picture of the stress evolution within arrays of through-silicon-vias (TSV) is developed using in-line Raman spectroscopy. A set of wafers with different TSV geometries and metal seed liner thicknesses is exposed to various annealing conditions. Monitoring the Si-Si phonon mode shift between the vias, the influence of via geometries and processing conditions on the stress in the Si substrate is characterized non-destructively. Compressive stress is found in close proximity to the TSVs post Cu fill, as expected. However, for arrays with small TSV pitches, the substrate does not fully relax in the space between the vias, but rather tensile stress accumulates within the arrays. This inter-via stress increases with decreasing TSV pitch, accumulates towards the center of the arrays, and strongly depends on the annealing conditions. High resolution Raman maps within the arrays reveal the full picture of stress distribution in the TSV arrays. By using different excitation wavelengths, the variation of the stress with depth in the Si wafer is probed. The findings demonstrate the value of in-line access to process-dependent stress information. This knowledge helps to define design ground rules for highest device performance or to maximize the useable area on the wafer for logic devices.

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