We investigated the improvement methods of the electrical characteristics and reliability of flexible low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) by optimizing the annealing process. We investigated the effect of annealing on the device properties via electrical measurement and density-of-state (DOS) analysis. The annealing temperature should be reduced for flexible LTPS TFTs compared to rigid devices because the range of the thermal stability of flexible substrate is narrower than that of the glass substrate. As the activation annealing temperature (Ta) decreased, the threshold voltage and field-effect mobility (μFE) decreased, and the subthreshold swing (SS) increased. When the post-annealing temperature (Tpa) decreased, μFE increased, and the changes in the other parameters were negligible. The DOS decreased with an increase in Ta and a reduction in Tpa. These results originated from ineffective dopant activation and defect curing due to the lower Ta and the enhanced hydrogen defect passivation at the lower Tpa. Therefore, flexible LTPS TFTs with reduced Ta values exhibited similar μFE values and lower SS values when the post-annealing process was omitted. Furthermore, removing the post-annealing process improved the reliability of the flexible LTPS TFTs with reduced Ta values under electrical stress. According to a hot-carrier instability analysis, defect passivation by hydrogen was more stable than defect curing with a higher Ta. Consequently, although Ta was low for flexible LTPS TFTs, the electrical performance and reliability could be improved by optimizing the post-annealing process.

We have investigated the degradation mechanism of solution-processed indium−gallium−zinc-oxide (IGZO) thin-film transistors. The threshold voltage shift (ΔV th ) followed a linear function under negative gate bias stress (NBS), while it showed a stretched-exponential behavior under positive gate bias stress. The slope of ΔV th for stress time was rarely changed with variations below 0.3 mV/s. The thickness of the fabricated IGZO layer (In 0.51 Ga 0.15 Zn 0.34 O) was approximately 10 nm. The Debye length (L D ) was larger than IGZO thickness (t IGZO ) due to the fully depleted active layer under NBS. Therefore, the degradation phenomenon under NBS was related to the adsorption at backchannel surface. The back-channel surface could be affected by the gate bias under NBS, and the molecules adsorbed at the IGZO layer were positively charged and induced extra electrons by NBS. We verified that the number of positively charged adsorbates had a proportional relationship with the ΔV th based on the twodimensional technology computer-aided design (TCAD) simulation. Furthermore, we investigated the degradation phenomenon with the ΔV th equation regarding the adsorbates, and the result confirmed that the adsorption process could cause the linear ΔV th . We experimentally confirmed the effect of back-channel surface by comparing the ΔV th between different atmospheric conditions and L D . Consequently, the reaction at the back-channel surface should be considered to develop the metal-oxide semiconductor devices.

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