No abstract

Forty-four different secondary alcohols, which can be classified into several types (II-IX), were tested as the substrates of ionic surfactant-coated Burkholderia cepacia lipase (ISCBCL) to see its substrate scope and enantioselectivity in kinetic and dynamic kinetic resolution (KR and DKR). They include 6 boron-containing alcohols, 24 chiral propargyl alcohols, and 14 diarylmethanols. The results from the studies on KR indicate that ISCBCL accepted most of them with high enantioselectivity at ambient temperature and with useful to high enantioselectivity at elevated temperatures. In particular, ISCBCL displayed high enantioselectivity toward sterically demanding secondary alcohols (types VIII and IX) which have two bulky substituents at the hydroxymethine center. DKR reactions were performed by the combination of ISCBCL with a ruthenium-based racemization catalyst at 25-60 °C. Forty-one secondary alcohols were tested for DKR. About half of them were transformed into their acetates of high enantiopurity (>90% ee) with good yields (>80%). It is concluded that ISCBCL appears to be a superb enzyme for the KR and DKR of secondary alcohols.

Abstract:The pulse-based charging method for battery cells has been recognized as a fast and efficient way to overcome the shortcoming of a slow charging time in distributed battery cells, which is regarded as a connection of cells such as the Internet of Things (IoT). The pulse frequency for controlling the battery charge duration is dynamically controlled within a certain range in order to inject the maximum charge current into the battery cells. The optimal frequency is determined in order to minimize battery impedance. The adaptation of the proposed pulse duty and frequency decreases the concentration of the polarization by sensing the runtime characteristics of battery cells so that it guarantees a certain level of safety in charging the distributed battery cells within the operating temperature range of 5-45 • C. The sensed terminal voltage and temperature of battery cells are dynamically monitored while the battery is charging so as to adjust the frequency and duty of the proposed charging pulse method, thereby preventing battery degradation. The evaluation results show that a newly designed charging algorithm for the implemented charger system is about 18.6% faster than the conventional constant-current (CC) charging method with the temperature rise within a reasonable range. The implemented charger system, which is based on the proposed dynamic frequency and duty control by considering the cell polarization, charges to about 80% of its maximum capacity in less than 56 min and involves a 13 • C maximum temperature rise without damaging the battery.

A particle filter (PF) has been introduced for effective position estimation of moving targets for non-Gaussian and nonlinear systems. The time difference of arrival (TDOA) method using acoustic sensor array has normally been used to for estimation by concealing the location of a moving target, especially underwater. In this paper, we propose a GPU -based acceleration of target position estimation using a PF and propose an efficient system and software architecture. The proposed graphic processing unit (GPU)-based algorithm has more advantages in applying PF signal processing to a target system, which consists of large-scale Internet of Things (IoT)-driven sensors because of the parallelization which is scalable. For the TDOA measurement from the acoustic sensor array, we use the generalized cross correlation phase transform (GCC-PHAT) method to obtain the correlation coefficient of the signal using Fast Fourier Transform (FFT), and we try to accelerate the calculations of GCC-PHAT based TDOA measurements using FFT with GPU compute unified device architecture (CUDA). The proposed approach utilizes a parallelization method in the target position estimation algorithm using GPU-based PF processing. In addition, it could efficiently estimate sudden movement change of the target using GPU-based parallel computing which also can be used for multiple target tracking. It also provides scalability in extending the detection algorithm according to the increase of the number of sensors. Therefore, the proposed architecture can be applied in IoT sensing applications with a large number of sensors. The target estimation algorithm was verified using MATLAB and implemented using GPU CUDA. We implemented the proposed signal processing acceleration system using target GPU to analyze in terms of execution time. The execution time of the algorithm is reduced by 55% from to the CPU standalone operation in target embedded board, NVIDIA Jetson TX1. Also, to apply large-scaled IoT sensing applications, we use NVIDIA Tesla K40c as target GPU. The execution time of the proposed multi-state-space model-based algorithm is similar to the one-state-space model algorithm because of GPU-based parallel computing. Experimental results show that the proposed architecture is a feasible solution in terms of high-performance and area-efficient architecture.

Most vendors of digital signal processors (DSPs) support a Harvard architecture, which has two or more memory buses, one for program and one or more for data and allow the processor to access multiple words of data from memory in a single instruction cycle. Also, many existing fixed-point DSPs are known to have an irregular architecture with heterogeneous registers, which contains multiple register files that are distributed and dedicated to different sets of instructions. Although there have been several studies conducted to efficiently assign data to multimemory banks, most of them assumed processors with relatively simple, homogeneous general-purpose registers. Thus, several vendor-provided compilers for DSPs that we examined were unable to efficiently assign data to multiple data memory banks, thereby often failing to generate highly optimized code for their machines. As a consequence, programmers for these DSPs often manually assign program variables to memories so as to fully utilize multimemory banks in their code. This paper reports on our recent attempt to address this problem by presenting an algorithm that helps the compiler to efficiently assign data to multimemory banks. Our algorithm differs from previous work in that it assigns variables to memory banks in separate, decoupled code generation phases, instead of a single, tightly coupled phase. The experimental results have revealed that our decoupled algorithm greatly simplifies our code generation process; thus our compiler runs extremely fast, yet generates target code that is comparable in quality to the code generated by a coupled approach.