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A common approach to debugging real-time DSP algorithms for FPGAs is to process a known data set in simulation. However, when large data sets are necessary or desired, simulations can take a significant amount of time. The goal of the architecture presented in this paper is to allow these algorithms to be easily debugged utilizing the Wireless Open-Access Research Platform (WARP). The WARP can be a valuable tool as its 2GB DDR2 memory module is capable of storing a large number of data samples for processing by its FPGA. Data can be obtained in realtime from an RF front end for processing, or loaded into the platform via an Ethernet connection. The WARP can also be used as a waveform capture and export tool, providing data for future processing runs or simulation. In this paper, the architecture's capabilities for signal capture and storage are demonstrated through the capture of a GPS signal from a RF front end and subsequent export of the digitized signal to Matlab for post-processing.