Abstract-The programming complexity of increasingly parallel processors calls for new tools to assist programmers in utilising the parallel hardware resources. In this paper we present a set of models that we have developed to form part of a tool which is intended for iteratively tuning the mapping of dataflow graphs onto manycores. One of the models is used for capturing the essentials of manycores that are identified as suitable for signal processing and which we use as target architectures. Another model is the intermediate representation in the form of a timed configuration graph, describing the mapping of a dataflow graph onto a machine model. Moreover, this IR can be used for performance evaluation using abstract interpretation. We demonstrate how the models can be configured and applied in order to map applications on the Raw processor. Furthermore, we report promising results on the accuracy of performance predictions produced by our tool. It is also demonstrated that the tool can be used to rank different mappings with respect to optimisation on throughput and end-to-end latency.

The programming complexity of increasingly parallel processors calls for new tools that assist programmers in utilising the parallel hardware resources. In this paper we present a set of models that we have developed as part of a tool for mapping dataflow graphs onto manycores. One of the models captures the essentials of manycores identified as suitable for signal processing, and which we use as target for our algorithms. As an intermediate representation we introduce timed configuration graphs, which describe the mapping of a model of an application onto a machine model. Moreover, we show how a timed configuration graph by very simple means can be evaluated using an abstract interpretation to obtain performance feedback. This information can be used by our tool and by the programmer in order to discover improved mappings.

This paper highlights the collaboration between industry and academia in research. It describes more than two decades of intensive development and research of new hardware and software platforms to support innovative, high-performance sensor systems with extremely high demands on embedded signal processing capability. The joint research can be seen as the run before a necessary jump to a new kind of computational platform based on parallelism. The collaboration has had several phases, starting with a focus on hardware, then on efficiency, later on software development, and finally on taking the jump and understanding the expected future. In the first part of the paper, these phases and their respective challenges and results are described. Then, in the second part, we reflect upon the motivation for collaboration between company and university, the roles of the partners, the experiences gained and the long-term effects on both sides.

IEEE 802.15.4 is a new enabling technology for low data rate wireless personal networks. This standard was not specifically designed for wireless sensor networks, but it has shown to be a good match with necessary requirements on low data rate, low power consumption and low cost. Unlike the former 802.11 standard, the MAC protocol specified in IEEE 802.15.4 can operate in two different modes: beacon-enabled mode or non-beacon enable mode. In beacon-enabled mode, nodes can exclusively allocate a number of guaranteed time slots, similar to a resource reservation scheme. Hence, the IEEE 802.15.4 MAC protocol have sufficient capabilities for supporting real-time communication. This paper presents the key features of IEEE 802.15.4 which makes it an attractive standard to use for real-time wireless sensor networks. Two real-time protocols extending the IEEE 802.15.4 standard are reviewed. The purpose of this paper is to present the state of the art on real-time support over IEEE 802.15.4 for wireless sensor networks and to discuss the possibilities on improvements on both the standard and the real-time protocols extending the standard.