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A functional fail of a DRAM is analyzed by using an analog output of the device as an input signal of a microscope. Local heating by an IR laser changes the pass/fail behavior and thus the analog output of the DRAM. Although the observed spots do not belong to the physical defect, they give a starting point for further electrical analysis leading to the root cause of the failure. The paper will present a case study on a state-of-the art DRAM device failing with a timing problem. Especially the test aspects as well as the setup for the temperature dependent localization will be described. Finally an interpretation of the results will be proposed.

Tungsten contacts mostly fail because of a defective bottom barrier which in turn may find its origin in technological problems with contact etch, barrier or tungsten deposition. Owing to the often unstable electrical properties of those contacts, detection in electrical test or non‐destructive localization techniques is time‐consuming or even unsuccessful. The reverse engineering techniques presented here supply 100% identification and localization of the failing contacts. They reveal a disturbed region under a barrier defect produced by the aggressive chemical reaction of fluorine radicals from WF6 deposition with silicon to the gaseous SiF4. The market contacts exceed the detection fails by far. Some failing contacts may slip through relaxed test conditions—the majority of them, though, still work and indicate a potential of reliability problems as could be demonstrated on chips failing the burn‐in. Thus, an analysis and classification of the contacts at the wafer level in the presented way allows an identification and first step to estimation of reliability yield risks.

The characterization of failure modes of DRAM is often straight forward if array related hard failures with specific addresses for localization are concerned. The paper presents a case study of a bitline oriented failure mode connected to a redundancy evaluation in the DRAM periphery. The failure mode analysis and fault modeling focus both on the root-cause and on the test aspects of the problem.

The electrical interface, in terms of a reliable, low ohmic and defined connection with the device or die is the most relevant aspect in the characterization of products. Bad or undefined contacts inhibit an exact assessment of the functionality. This paper describes different contact related failures analyzed in our lab and gives the solutions we used to solve the problems. Especially an electroless (nickel)-gold plating method has been optimized and is described in details. Low ohmic and reliable contacts can be produced; the paper shows several applications to improve the contact quality in different domains of the failure analysis business