We present a simple, one-pot approach for synthesizing ultrafine platinum (Pt) nanoclusters (NCs) under alkaline conditions using lysozyme (Lys) as a template. From the analysis of the nanoclusters by matrix-assisted laser desorption/ionization time-of-flight mass spectrometry, Lys VI-stabilized Pt NCs majorly consisted of Pt4 clusters. The formation of Pt NCs was confirmed using X-ray photoelectron spectroscopy and Fourier-transformed infrared spectroscopy. The maximal fluorescence of Pt NCs appears at 434 nm with a quantum yield of 0.08, a fluorescence lifetime of 3.0 ns, and excitation-dependent emission wavelength behavior. Pt NCs exhibit an intrinsic oxidase-like activity because Pt NCs can catalyze O2 oxidation of organic substrates through a four-electron reduction process. Compared with larger Pt nanoparticles, the Pt NCs produce substantially greater catalytic activity in the O2-mediated oxidation of 2,2'-azino-bis(3-ethylbenzothiazoline-6-sulphonic acid), 3,3',5,5'-tetramethylbenzidine, and dopamine.

No abstract

This paper presents a complete design of 100GbE chipsets including gearbox TX/RX, LDD and TIA/LA arrays. Figure 7.3.1 shows the architecture, where 10×10Gb/s input data is serialized into 4×25Gb/s bit stream by a 10:4 serializer (i.e., gearbox TX). A 4-element LDD array subsequently drives 4 laser diodes, emitting 850nm light into 4 multimode fibers (MMFs). After traveling over 100m, these optical signals are captured and transformed into electrical domain by means of photo diodes (PDs) and a TIA/LA array. A 4:10 deserializer (gearbox RX) recovers the clock and data, and restores the data sequences into 10×10Gb/s outputs. In applications, gearbox TRX and optical frontends (i.e., LDD and TIA/LA arrays) may be separated by several inches in order to fulfill system-level integration.The gearbox TX consists of a multi-frequency multi-phase clock generator and two identical sets of 5:2 serializer, each one including five 1:4 DMUXes and four 5:1 MUXes. Modified from [1] with even larger bandwidth, the FFE uses a halfrate structure. A built-in PRBS generator is introduced to facilitate testing, which provides 5 independent 10Gb/s data inputs with length 2 7 −1. Gearbox RX design follows the basic structure of [2], which incorporates pre-amplifiers (with gain of 0 to 20dB), mixer-based CDRs [3], 1:10 DMUXes and 4:1 MUXes. The CDR adopts a full-rate linear phase detection structure that has been proven (in silicon) to achieve data rate up to 40Gb/s. In addition to the existing deskew circuit that removes phase offset within 1 bit, we further introduce a bit-alignment circuit in front to fix up to ±7 bits of misalignment due to optical length difference.The 5:1 MUX circuit is illustrated in Fig. 7.3.2(a), which is realized as a 5-input transmission-gate sampler operated by rail-to-rail data and clocks. Five TSPC FFs with a NOR-gate feedback produce five 20% duty-cycle clocks CK 1~5 for proper sampling. Figure 7.3.2(b) reveals the bit-alignment design, where a 15b shift register governed by 4b control stores data stream. Based on the control signal, 5 consecutive bits out of [−7,..,,0,..,7] can be taken as data output and be set to the subsequent circuit for processing. Since 100GbE only needs fiber channel of 100 to 300m, a 15b phase shifter is sufficient in most cases. To minimize clock phase noise, we realize TX clock generator as a two-stage subharmonically-injection-locking PLL [4] as depicted in Fig. 7.3.2(c). Fixed delays ΔT 1 to ΔT 4 are inserted to ensure that injections always locate at save zone (approximately 187˚) over PVT variations.The optical frontend also involves considerable circuit techniques. Figure 7.3.3 shows the VCSEL driver design, whose core is actually a 2-tap fractional FFE with tunable delay (ΔT) and pre-emphasis factor (α). Here, main cursor (I 0 ), precursor (I −1 ), and bias current (I DC ) are summed up through M 1~M5 single-endedly and are fed into the diode. These currents are mirrored from bandgap reference to maintain fixed amounts over PVT variations. Neglecting I DC , the 2-tap FFE's r...

No abstract