This paper presents the VLSI implementation of a lattice-reduction-aided (LRA) detection system. The proposed system includes a QR decomposition, lattice reduction (LR) processor, and sorting-reduced (SR) K-best detector for 8 × 8 multiple-input multiple-output (MIMO) systems. The bit error rate of the proposed MIMO detection system only incurs approximately 3 dB of implementation loss compared with optimal maximum likelihood detection with 64-quadratic-amplitude modulation. The proposed processor can also support different throughput requirements by adjusting the stage number of LR. The SR K-best detector can achieve 3.1 Gb/s throughput with 0.24-ns latency. The throughput of the system reaches 585 Mb/s if one channel preprocessing can support 72 symbol detections. The corresponding energy per bit is 63 pJ/bit, which is the smallest value achieved to date. This paper presents the first VLSI implementation of a complete LRA K-best detector with an 8 × 8 dimension.Index Terms-K-best detector, lattice reduction (LR), multipleinput multiple-output (MIMO) detection.

This study presents a joint QR decomposition and lattice reduction processor for 8 × 8 multiple-input multipleoutput (MIMO) systems. The proposed algorithm enhances the BER performance by lattice reduction and reduces the hardware cost by sharing computation units and removing redundant operations. This processor can be reconfigured as three different modes, including joint QR decomposition and lattice reduction, lattice reduction, and QR decomposition. The proposed processor was implemented in TSMC 90nm 1P9M CMOS technology. The maximum throughput is 1.1 M matrix/s for QR decomposition, and 0.5 M matrix/s for the lattice reduction, and 0.33 M matrix/s for the joint QR decomposition and lattice reduction at a power consumption of 31.2 mW. The energy efficiency achieves 0.18nJ/matrix for the 8 × 8 MIMO preprocessing including both QR decomposition and lattice reduction.

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