For the first time, a dynamic negative bias temperature instability (DNBTI) effect in p-MOSFETs with ultrathin gate oxide (1.3 nm) has been studied. The interface traps generated under NBTI stressing corresponding to p-MOSFET operating condition of the "high" output state in a CMOS inverter, are subsequently passivated when the gate to drain voltage switches to positive corresponding to the p-MOSFET operating condition of the "low" output state in the CMOS inverter. Consequently, this DNBTI effect significantly prolongs the lifetime of p-MOSFETs operating in a digital circuit, and the conventional static NBTI (SNBTI) measurement underestimates the p-MOSFET lifetime. A physical model is presented to explain the DNBTI. This finding has significant impact on future scaling of CMOS devices.Index Terms-Annealing, CMOSFETs, negative bias temperature instability (NBTI), semiconductor-insulator interfaces, ultrathin gate oxide.

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