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Negative Bias Temperature Instability (NBTI) is one of the major reliability concerns for pMOSFETs as the transistor gate oxide thickness is scaling down. Incorporating fluorine into the gate oxide is a well-known method to effectively suppress NBTI. The efficiency and mechanism are studied carefully in earlier reports. The focus of this paper is to analyze how the fluorine incorporation impacts on device performance and process integration. Different fluorine implantation conditions and their impacts on NBTI lifetime, device performance and process integration were studied and analyzed. The results demonstrated that fluorine implants could prolong pMOSFETs NBTI lifetime, but would reduce threshold voltage and degrade Ion-Ioff performance. Meanwhile, process defects were found if the F2 dose in the active area is greater than a certain value. Analysis and discussions are carried out to understand those phenomena.

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Device with shallow trench isolation (STI) has inverse narrow width effect (INWE), that is the threshold voltage of narrow width transistors is lower than that of large width transistors. The conventional methods of improving INWE focus on STI module optimization, such as active area corner rounding, step height and divot control. In this paper, a new approach by implant optimization is proposed to improve INWE. For low power PMOS device, phosphorus halo implant is often used for its lower diode leakage characteristics. This paper reports optimized dual halo implant approach with both arsenic and phosphorus implants to improve INWE. This approach gives larger Gm*Rout and lower digital product chip stand-by current without reliability degradation.