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In the last five decades, the number of transistors on a chip has increased exponentially in accordance with the Moore's law, and the semiconductor industry has followed this law as long-term planning and targeting for research and development. However, as the transistor feature size is further shrunk to sub-14nm nanometer regime, modern integrated circuit (IC) designs are challenged by exacerbated manufacturability and reliability issues. To overcome these grand challenges, full-chip modeling and physical design tools are imperative to achieve high manufacturability and reliability. In this paper, we will discuss some key process technology and VLSI design co-optimization issues in nanometer VLSI.

Recently, directed self-assembly (DSA) has emerged as a promising lithography solution for cut manufacturing. We perform a comprehensive study on the DSA aware mask optimization problem to provide a DSA friendly design on cut layers. We first formulate the problem as an integer linear programming (ILP) to assign cuts to different guiding templates, targeting both conflict minimization and line-end extension minimization. As ILP may not be scalable for very large size problems, we then propose two speed-up strategies. The first one is to decompose the initial problem into smaller ones and solve them separately, followed by solution merging without much loss of quality. The second one is using the set cover algorithm to decide the DSA guiding pattern assignment, and then legalize the template placement. Our approaches can be naturally extended to handle arbitrary DSA guiding template patterns with complicated shapes. Experimental results show that our methodologies can significantly improve the DSA friendly, i.e., both the unresolved pattern number and the lineend extensions can be reduced.

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