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Analog compute schemes as well as compute-in-memory have emerged in an effort to reduce the increasing power hunger of convolutional neural networks, which exceeds the constraints of edge devices. Memristive device types are a relatively new offering with interesting opportunities for unexplored circuit concepts. In this work, the use of memristive devices in cascaded time domain compute-in-memory is introduced with the primary goal of reducing size of fully unrolled architectures. The different effects influencing determinism in memristive devices are outlined together with reliability concerns. Architectures for binary as well as multi-bit multiply and accumulate cells are presented and evaluated. As more involved circuits offer more accurate compute result, a trade-off between design effort and accuracy comes into the picture. To further evaluate this trade-off, the impact of variations on overall compute accuracy is discussed. The presented cells reaches an Energy/OP of 0.23 fJ at a size of 1.2 µm 2 for binary and 6.04 fJ at 3.2 µm 2 for 4x4 bit multiply and accumulate operations.

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