No abstract

Wearable and implantable medical sensors have been investigated continuously in recent years to provide better diagnostics and monitoring for personal health care. Much attention has been drawn to the establishment of the ubiquitous body area network (BAN) to reliably connect the body sensors and collect the sensor data in real time. Electric-field intrabody communication (EF-IBC) is a promising physical link technology for the body area network. Compared to existing wireless technologies, EF-IBC fits the body characteristics better and is able to achieve higher data rate with less transmission power. EF-IBC relies on the parasitic capacitive coupling between the transmitter and the receiver to close the signal circuit loop. With this parasitic coupling, EF-IBC links can be influenced by the environment. However until now, there is lack of systematic research on various environment coupling effects to the EF-IBC channel. In this paper, environment effects on the EF-IBC channel are comprehensively studied. The interference from the nearby EF-IBC channel is investigated for the first time to gain useful insights into the establishment of the BAN with EF-IBC. The FEM model is also established to explain the mechanism of the capacitive return path.

Array sensors require a high-performance analog-todigital converter (ADC) array with small area and low power. Successive-approximation register (SAR) ADC has good potential for ADC array due to its simple analog circuits. However, SAR ADCs with 10-b resolution and higher normally need a large capacitor array due to the stringent matching requirement. The large capacitor array also limits the ADC dynamic performance. The capacitor mismatch has been compensated by analog calibration techniques. In this work, a novel digital calibration method is developed for SAR ADC based on dithering. With dithering, weights of most significant bit (MSB) capacitors can be measured accurately so that very small capacitors can be used in the SAR ADC due to the relaxed matching requirement. A modified bit-cycling procedure is developed to avoid the code gaps caused by capacitor dithering. This calibration technique requires no analog calibration overhead and simple digital decoders. The technique is implemented in an ADC array design including 256 SAR ADCs for a high-speed CMOS imaging sensor in a 0.18-m CMOS process. The 10-b SAR ADC is designed with the minimum capacitor array size in the process. A single SAR ADC only occupies15 m 710 m. Sampling at 768 kS/s, peak DNL and peak INL of the original ADCs averaged across the array are 0.82 least significant bit (LSB) and 3.85 LSB, respectively. For a signal close to the Nyquist frequency, original ADCs have 7.96-b average ENOB. After calibration with dithering, ADCs have 0.55-LSB peak DNL and 0.77-LSB peak INL averaged across the array. The average ENOB improves to 9.83 b. Compared with the benchmark 10-b SAR ADCs, this design is the most area-efficient design. In this work, the calibration decoders are implemented off-chip. With a sample-and-hold amplifier, the calibration method can run in the background.Index Terms-ADC array, analog-to-digital converter (ADC), digital calibration, dithering, successive-approximation register (SAR).