Abstract-Reed-Solomon (RS) codes play an important role in providing the error correction and the data integrity in various communication/storage applications. For high-speed applications, most RS decoders are implemented as dedicated application-specified integrated circuits (ASICs) based on parallel architectures, which can deliver high data throughput rate. For lower-speed applications, the RS decoding operations are usually performed by using fine-grained processing elements (PE) controlled by a programmable digital signal processing (DSP) core, which provides high flexibility. In this paper, we propose a novel -PE multisymbol-sliced (MSS) RS datapath structure. The -PE RS architecture is a highly scalable design and can be dynamically reconfigured at 1-PE, 2-PE,. . .2-PE, and -PE modes to deliver necessary data throughput rate. With the help of the gated-clock scheme to turn off the idle PEs, the proposed runtime configurable ASIC design provides good tradeoff between the data throughput rate and the power consumption. Hence, it can save energy to extend the battery life of the portable devices. We demonstrate a prototyping design using 4 PEs by using UMC 0.18-m CMOS technology. The design can be dynamically reconfigured to be operated at 1-PE, 2-PE, and 4-PE modes, with performance of 140 Mb/s at 18.91 mW, 280 Mb/s at 28.77 mW, and 560 Mb/s at 48.47 mW, respectively. Compared with existing RS designs, the proposed -PE RS decoder has better normalized area/power efficiency than most DSP-type and ASIC-type RS designs. The reconfigurable feature makes our design a good candidate for the error control coding (ECC) unit of the storage system in power-aware portable devices.

Reed-Solomon (RS) codes play an important role in providing error protection and data integrity. Many researches of RS decoder are implemented in parallel architecture, which can perform the highest data throughput rate in all RS decoder architectures. However, for some specifications such as Digital Video Broadcasting system (DVB), the requirement of data throughput rate is very low and a low-power folding architecture is enough to achieve the data throughput rate requirement. The hardware cost of folding architecture is also comparably much smaller than the hardware cost of parallel architecture. In this paper we present a design of a scalable RS codec processor design with a reconfigurable architecture. The reconfigurable architecture has good flexibility for tradeoff between the data throughput rate and power consumption. Compared with the DSP type architecture, the proposed reconfigurable architecture can perform higher data throughput rate with shorter latency. Besides, with combination of two RS processor engines, we can easily double the performance with the scalable design. This good scalability is another advantage of our proposed reconfigurable architecture.

This paper proposes an area-efficient architecture to implement the Modified Euclidean algorithm (MEA), which is frequently used in Reed-Solomon decoders. We present the new ME architecture to achieve highthroughput rate and reducing hardware complexity. We propose a folding architecture to reduce the hardware complexity about 50%' compared to the fully parallel architecture. The Modified Euclidean algorithm has been implemented in 0.18-pm CMOS technology with 1.8V supply voltage. The results show that total number of gates is about 20K and it has a data processing rate of 3.2Gbids at clock frequency of 400 MHz. The proposed area-efficient architecture can be readily applied to 10Gbase-LX4 optical communication systems.

In this paper, an implcmentation of a baseband demodulator for DVB-T systems is presented. We build several multimode SIPs and integrate them into a DVB-T baseband demodulator. 'Ihe demodutator includes FFT, channel estimator, channel equalizer, deinterleavers, PECs, and descrambler. We utilize Simulink to establish a system-level simulation environment and USC this system simulation model to evaluate performance. Moreover, the modules we used to integrate thc demodulator are multimode SIPs so that the demodulator is able to meet the multimode feature of not only DVB-T (2K and SK modes) but DVB-H (4K mode) systems.