Knowledge transfer is a key function in software development. Software tool development is an important skills in the software engineering. However, generic teaching courses are hard to evaluate the integrated development skills from undergraduate students. This paper proposed a continuous collaboration model (CCM) and a view-based semi-automatic tool, OpenNeeds, develop and run as an Eclipse plug-in to proceed the functional requirements' analysis. These selected methods and tools include programming languages, markup language, information exchange standards, modeling language, model-view-controller (MVC) software framework, virtual machine handling, interface development environment, version control platform, knowledge management, software documentation, and software unit tests. The MVC tool can simply manipulate several requirement-related graphical components, such as mind view and use case view. The lateral thinking approach is adapted in grid view to assist in analyzing other potential requirements from the original ones. Subsequently, the source codes of this tool are opened and can be distributed via the Eclipse Public License from the OpenFoundry and Github repositories. There are three professors who come from two distinct colleges to share their learning experiences. Meanwhile, 26 and 27 college students attend this team in the first and second year, respectively. Professors can truly understand the fortes of the individual attendee through the attending performance and promote his/her merits in the future tasks. Further, their industrial practices and related outcomes might disclose that the proposed CCM is feasible and trustable in college environment, especially for the software development activities in the software engineering field. ß 2015 Wiley Periodicals, Inc. Comput Appl Eng Educ 24:131-143, 2016; View this article online at wileyonlinelibrary.com/journal/cae;

With the rapid escalation in design complexity of real-time embedded software, application frameworks have become an almost indispensable tool because they greatly ease the work of a designer by performing tedious tasks on behalf of a designer and by reusing semicomplete application codes. To ensure code quality and reliability, computer-aided analysis is also performed for the generated application software in some frameworks. However, when the target is real-time embedded systems, the correctness of the software in terms of satisfying all user-given real-time and embedded constraints becomes a primary objective for such frameworks. To guarantee correctness, formal verification in the form of model checking is a viable solution due to its full automation capability. Nevertheless, little is known from either the existing literature or industrial experience on how formal verification can be integrated into an object-oriented application framework, whose primary purpose was previously only to design and generate application software. This work contributes to the state-of-art technology by showing how a design framework and a verification framework can be integrated. Three main issues are tackled: (i) what to verify?; (ii) when to verify?; and (iii) how to verify? As a solution to these three issues the authors propose a mapping from the object-oriented model to a formal model, a schedule-verifymap strategy and a compositional verification methodology, respectively. These have been implemented in a component-based framework and experiments performed to illustrate their feasibility. Due to the incorporation of industry de-facto standards such as real-time unified modelling language and real-time Java, in the proposed techniques it should now be possible for an engineer to gain access to theoretically proven formal verification technologies that would otherwise be considered to be inaccessible to an engineer unskilled in verification techniques.

Advancements in hardware and software technologies have made possible the design of real‐time systems and applications where stringent timing constraints are imposed on critical tasks. The design of such systems is more complex than that of temporally unrestricted systems because system correctness depends on the satisfaction of functional as well as temporal requirements. To aid users in correctly and efficiently designing systems, object‐oriented frameworks provide a useful environment for significant reuse and reduction in design effort. In contrast to other application domains, there has been relatively little work on an application framework for the design of real‐time systems. Facing the growing need for real‐time applications, we propose a novel application framework called SESAG, which consists of five components, namely Specifier, Extractor, Scheduler, Allocator, and Generator. Within SESAG, several design patterns are proposed and used for the development of real‐time applications. A new evaluation metric called relative design effort is proposed for evaluating SESAG. Experiences in using SESAG show a significant increase in design productivity through design reuse and a significant decrease in design time and effort. Two complex application examples have been developed using SESAG and evaluated using the new evaluation metric. The examples demonstrate relative design efforts of at most 18% of the design efforts required by conventional methods. Copyright © 2005 John Wiley & Sons, Ltd.

Embedded real-time applications are often built from scratch on a trial-and-error basis, which leads to sub-optimal designs with latent errors that are not detectable in early stages of use or deployment and often incurs prolonged time-to-market. A new application framework called Verifiable Embedded Real-Time Application Framework (VERTAF) is proposed for embedded real-time application development, with the aim of reducing design errors and increasing design productivity. VERTAF is an integration of three technologies, namely object-oriented technology, software component technology, and formal verification technology.VERTAF consists of five software components: Implanter, Modeler, Scheduler, Verifier, and Generator. Experiences of using VERTAF show a significant increase in design productivity through design reuse, and a significant decrease in design time and effort through design verification. An example shows a relatively low design effort on the part of the designer using VERTAF.

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