We present the first demonstration of a III-V MOSFET heterointegrated on a large diameter Si substrate and fabricated with a VLSI compatible process flow using a high-k/metal gate, self-aligned implants and refractory Au free ohmic metal. Additionally, TXRF data shows that with the correct protocols III-V and Si devices can be processed side by side in the same Si fabrication line The L g = 500 nm device has a excellent drive current of ~450 µA/µm and intrinsic transconductance of ~1000 µS/µm indicating that III-V VLSI integration is a serious contender for insertion at or beyond the 11 nm technology generation.

Non-planar transistor architectures, such as tri-gates or "FinFETs", have evolved into important solutions to the severe challenges emerging in thermal and power efficiency requirements at the sub-32 nm technology nodes. These architectures strain traditional dimensional metrology solutions due to their complex topology, small dimensions, and number of materials. In this study, measurements of the average dielectric layer thickness are reported for a series of structures that mimic non-planar architectures. The structures are line/space patterns (≈ 20 nm linewidth) with a conformal layer of sub-15 nm thick high-k dielectric. Dimensions are measured using a transmission X-ray scattering technique, critical dimension small angle X-ray scattering (CD-SAXS). Our test results indicate that CD-SAXS can provide high precision dimensional data on average CD, pitch, and high-k dielectric layer thickness. CD-SAXS results are compared with analogous data from both top-down scanning electron microscopy and cross-sectional transmission electron microscopy. In addition, we demonstrate the capability of CD-SAXS to quantify a periodic deviation in pitch induced by an imperfection in the phase shift mask.

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High electron mobility III-V materials are strong candidates for nMOS transistors at the 11 nm technology node and beyond. Integrating III-V materials with Si (III-V/Si) is an attractive approach because it leverages the current Si-based manufacturing platform. However, the large lattice mismatch between III-V and Si leads to defects in the channel and compromises device performance and reliability. This paper explores two inline X-ray based characterization techniques, high resolution X-ray diffraction (HRXRD) and X-ray diffraction imaging (XRDI), to characterize defects in novel III-V/Si structures. The benefits and limitations of these techniques will be discussed.

Integrated circuits have already entered the world of nanoelectronics. According to the International Technology Roadmap for Semiconductors, the industry will be extending CMOS technology through new materials and device structures for at least the next fifteen years. During that time, the gate length of nanotransistors will shrink to less than 10 nm. The electrical properties of nano-transistors will move into regime of short channel devices where new physics will result in changes in transistor operation. The number of transistors in a single IC is already approaching a number that results 2 billion functions per IC by 2010. Nano-sized features and high density will challenge metrology and characterization and most certainly move measurement further into the world of nanotechnology. Beyond CMOS, new nano-technology based devices are being considered as a means of continuing the rapid pace of technological innovation in electronics.